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K60 hangs waiting for MCG_S_IREFST

Question asked by Marlon Smith on Nov 13, 2015
Latest reply on Nov 17, 2015 by Mark Butcher

Hi everyone,

 

I'm using a k60 that is supplied with an external 50MHz clock.  I used Processor Expert to generate code to set up the clocks, but the code hangs while it's waiting for the FLL reference clock to be supplied by the external reference clock.  I've looked through the code and I can't find anything wrong.  Here's the code I'm using:

 

/*** ### MK60DN256VLQ10 "Cpu" init code ... ***/

    /*** PE initialization code after reset ***/

 

    /* System clock initialization */

    /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |

                SIM_CLKDIV1_OUTDIV2(0x01) |

                SIM_CLKDIV1_OUTDIV3(0x03) |

                SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */

    /* SIM_SCGC5: PORTA=1 */

    SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */

    if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {

    /* PMC_REGSC: ACKISO=1 */

    PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */

    }

    /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |

                SIM_CLKDIV1_OUTDIV2(0x01) |

                SIM_CLKDIV1_OUTDIV3(0x01) |

                SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */

    /* SIM_SOPT2: PLLFLLSEL=0 */

    SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */

    /* SIM_SOPT1: OSC32KSEL=3 */

    SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */

    /* PORTA_PCR18: ISF=0,MUX=0 */

    PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));

 

    /* Switch to FBE Mode */

    /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */

    MCG_C2 = MCG_C2_RANGE0(0x02);

    /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

    OSC_CR = OSC_CR_ERCLKEN_MASK;

 

    /* MCG_C7: OSCSEL=0 */

    MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);

    /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

    MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);

    /* MCG_C4: DMX32=0,DRST_DRS=0 */

    MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));

    /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x0F */

    MCG_C5 = MCG_C5_PRDIV0(0x0F);

    /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */

    MCG_C6 = MCG_C6_VDIV0(0x08);

 

    while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */     <<<<<-------------    THIS LINE HANGS FOREVER

    }

    while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

    }

 

    /* Switch to PBE Mode */

    /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */

    MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x08));

    while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */

    }

    while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */

    }

    /* Switch to PEE Mode */

    /* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

    MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);

    while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */

    }

    /*** End of PE initialization code after reset ***/

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