Hi all,
Regard to PCIe of L3.14.28 Yocto i.MX6Q SabreSD BSP, I'm confusing now.
* I believe i.MX6 support PCIe RC mode only so far.
* According to the release note, there is PCIe EP/RC validation system.
* I found a patch here:
https://community.freescale.com/docs/DOC-95014
https://community.freescale.com/message/544463
* This system realized following features, I think.
EP can access the memory of RC.
RC can access the memory of EP.
Let me confirm some use cases as following, after patch applied;
(Q1) Can FPGA(EP mode) access the 16MB memory of iMX6(RC mode)?
(Q2) Can iMX6(RC mode) access the 256MB memory of FPGA(EP mode)?
(Q3) Can iMX6(EP mode) access the 256MB memory of FPGA(RC mode)?
(Q4) Can FPGA(RC mode) access the 16MB memory of iMX6(EP mode)?
I hope at least fist 2 answers are YES and BSP already supported them.
Can anyone help me?
Hi torus1000
please refer to link below describing BARs limit for memory regions
Best regards
igor
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I know that Q2 works on Linux freescale 3.0.35 and i.MX6 Solo ARM processor.