I got a problem of MK30F64VLH10 CMP with ADC module, following is the detail:
ADC Module: ADC0 and ADC1
Every second, there are 16 sampling groups, in each sampling group, there are 9 sampling points, in each sampling points, the ADC0 work in differential 16-bit mode and ADC1 work in single-ended 16-bit mode
CMP Module: CMP1:
Signal in CMP1_IN1: 50Hz sine wave
Signal in CMP1_IN3: Reference voltage
When the ADC module is working, the output of CMP signal is getting bad that means there is a lots of output in the zero crossing point. But if disabled ADC module, the CMP output is OK.
The attached files are the signal got from CM1_OUT disabled and enabled ADC module.