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MK30F64VLH10 CMP Problem

Question asked by Martin Zhang on Sep 27, 2015
Latest reply on Sep 28, 2015 by Martin Zhang



I got a problem of MK30F64VLH10 CMP with ADC module, following is the detail:


MCU:                                    MKV30F64VLH10

ADC Module:                    ADC0 and ADC1

Every second, there are 16 sampling groups, in each sampling group, there are 9 sampling points, in each sampling points, the ADC0 work in differential 16-bit mode and ADC1 work in single-ended 16-bit mode

CMP Module:                    CMP1:





Signal in CMP1_IN1: 50Hz sine wave

Signal in CMP1_IN3: Reference voltage


Issue Description:

When the ADC module is working, the output of CMP signal is getting bad that means there is a lots of output in the zero crossing point. But if disabled ADC module, the CMP output is OK.


The attached files are the signal got from CM1_OUT disabled and enabled ADC module.



Best Regards,

Martin Zhang