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Kinetis L: Clock Gating - Using Partial STOP1

Question asked by PETER TWISS on Sep 8, 2015
Latest reply on Sep 14, 2015 by PETER TWISS



Interested in reducing as much power a possible to my system while ADC is able to take a measurement. This requires Partial STOP1, with clock gating control...only enabling ADC clock, and disabling clocks from all peripherals and sleeping processor.


I found this post explaining STOP1, which I just learned of, and I can see in PE how this is enabled, etc:


Operation modes in Processor Expert


But how is the gate controlling done? I do not see additional option menus pop up once enables in PE? Am I going to have to dig through registers on my own or is there some options/directions guidance that can be given? Also, does PE generate the needed code to implement clock gating on specific peripherals?