There's this "MX28_DDR2_Escape_routing_example" layout file... I really can't recall where I got it, but it's somehow related to AN4215 ("2-Layer Escape Routing Example" section).
I this layout example, I found something that I don't understand:
Pins K14 and K15 are shorted together, and L15 is tied to VDD_EMI. However: according to IMX28 pinout, the pins that do need to be shorted (EMI_DDR_OPEN and EMI_DDR_OPEN_FB) are K14 and L15, whereas K15 shall be tied to VDD_EMI (1V8).
There are others discrepancies in the IMX pinout: for instance, M11, M12 pins are connected to GND. However, according to the datasheet, those pins are to be connected to VDD...
Can anyone confirm those discrepancies?
Thanks indeed, best regards