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DDR3 Adress Lenght of iMX 6q SABRE SDB

Question asked by Ahmet Bolu on May 26, 2015
Latest reply on May 31, 2015 by Yuri Muhin

Hello,

After reading another thread (About layout of address and command signal in i.MX6 SABRE-AI. ), now i can understand main guideline is hardware development guide not SABRE design Because some address lenghts are beyond the limit of HDG(Hardware Design Guide). But i also have some additional questions about lenght matching:

1) What is the meaning of +-25?Is it allowed to use 975 mil 1000 mil and 1025 mil signals together in same address group? So it means 50 mil difference is allowed?

2) As we know the propogation delay of signals are different in microstrip (on top or bottom layers) with stripline(on internal layers) So our calculations shows that (for our pcb structure) the address lenght of 1000 mil signal on internal layer is equivalent to 1078 mil signal lenght of top/bottom layer. So what could be the best aproach to match these signals?:

*Match exact lenghts(without taking into acount the propogation delays)

*Match propogation delays (equivalent lenght)

3) Since some signals are not following the same structure of the address lines, do we have to taking via lenghts into considerations? Lets say an address line use one more via or one has Layer1 to Layer8 cross and one has Layer3 to Layer6. What would be the best approach?

@Thanks in advance...

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