we are connecting an i.MX6DQ with a FPGA through the EIM bus and we need help to find the register settings used to get maximum performance for synchronous write operations on that interface?
We use the bus in 16-bit synchronous multiplexed mode. Our register settings are:
EIM_CS0GCR1 = 0x0191103F EIM_CS0GCR2 = 0x00001000 EIM_CS0RCR1 = 0x01000000 EIM_CS0RCR2 = 0x00000000 EIM_CS0WCR1 = 0x01000000 EIM_CS0WCR2 = 0x00000000
Because we use the bus in multiplexed mode to get maximum performance the burst length on a write has to be maximized. What settings is needed in order to get the as many data as possible per address in one CS cycle? What can we expect to be the maximum amount of data within a CS cycle?
We can also confirm from measurements that there are long delays between CS cycles that previously has been discussed in https://community.freescale.com/message/428151 and https://community.freescale.com/message/491788. This is the reason to get as long CS cycles as possible to increase performance.