Hi Nori,
Each of these bits from USBOH1_UTMI_CLK_VLD register correspond to each USB controller, as the i.MX50 has one OTG controller and one Host-only controller (H1):
So, the values of these read-only bits should match with your hardware configuration.
Hope this will be useful for you.
Best regards!
/Carlos
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Hello Carlos,
I checked the two bits in USBOH1_UTMI_CLK_VLD with OBDS.
src/mx50/hardware.c
int is_utmi_clk_ready(void)
{
while (!((*(volatile u32 *)USBOH1_UTMI_CLK_VLD) & (0x1 << 7))) ; //host1 utmi clock is not OK?
return 1;
}
This function is waitng for the bit 7 to be ready.
From RM, the bit 7 is for OTG PHY, not for HOST PHY.
I think the description of RM is reverse...
The above check passes anyway because this test program enables both PHYs as follows.
void usb_clock_enable(void)
{
*(volatile u32 *)(CCM_CCGR2) |= 0x0C000000; //enable USBOH3_IPG_AHB
*(volatile u32 *)(CCM_CCGR4) |= 0x00003C00; //enable PHY1 and PHY2 clock
*(volatile u32 *)(USB_CLKONOFF_CTRL) = 0; //enable AHB clock for HOST1 and OTG
}
So I modified to enable only HOST PHY(PHY1).
void usb_clock_enable(void)
{
*(volatile u32 *)(CCM_CCGR2) |= 0x0C000000; //enable USBOH3_IPG_AHB
*(volatile u32 *)(CCM_CCGR4) &= 0xFFFFCBFF; //enable PHY1 only clock
*(volatile u32 *)(USB_CLKONOFF_CTRL) = 0x20000; //enable AHB clock for HOST1 only
}
Then the host1 utmi clock check passed as well.
Seems like bit 7 is for HOST PHY.
I bet RM is wrong...
Best regards,
Nori Shinozaki
