I2C SMB and Glitch Filter Questions

[jackjamieson]

We are having some detail questions regarding Kinetis 10 MCU's I2C controller, registers and its capability.

We are using  MK10DN512VLQ10 and MQX OS 4.0 with Interrupt Based I2C driver provided by the OS.
Basically, we are having some noise on the I2C bus and want to recover/reset from abnormal I2C error conditions.

According to the Chapter 45 of the K10P144M100SF2V2RM, there are I2C0_SMB & I2C1_SMB registers to detect conditions of SCL and SDA states. But, the reference manual are somewhat confusing and we are not 100% sure how to use those registers to detect I2C error conditions. Belows are the list of the question I have:

(1)   Is there any way to reset only the I2C controller modules without resetting the whole K10 ? 
(2)   How can we use the I2Cx_SMB ?
        a.  SLTF   -> Is this for I2C master mode, slave mode or both ?  What is the "LoValue" ?  Is this for SLTL counter loaded with I2C bus clock frequency counter ?
       b.  SHTF2 -> Is this for the condition that the I2C slave is holding the SDA ? I2C slave mode/master mode ?  
       c.   What value do we have to load into I2Cx_SLTH and I2Cx_SLTL  ?
       d.   How the glitch filter is operating  I2Cx_FLT ?   
       d.   Is there any application note or sample code that shows how to use the I2C SMB capabilities and glitch filter ?

Any help would be greatly appreciated!

[RadekS]

Hi John,

1. You can try clear and set again I2Cx_C1[IICIE] bit. This will not reset registers to default values, but it should reset internal state machine to default state. Unfortunately I didn’t test it.
2. In general, I would like to recommend do not use FACK, ALERTEN and SIICAEN features. These features have sense only in some cases and software workaround for rest situations brings additional overhead which could minimize benefit of these hardware solutions.

          a) SLTF is for both modes. When this bit is set, master has to conclude that a defective device is holding the clock low indefinitely or slave has to conclude that master is intentionally trying to drive devices off of the bus. “LoValue” is name of value which you write into SLTH and SLTL registers. This name is used in calculations for SCL High Timeout Flags. The SMBus operating frequency range is 10 kHz to 100 kHz. Because a minimum speed needs to be maintained in this communication, a slave can hold SCL low for only a specified amount of time before the master times out and issues a stop condition. A slave can hold the clock low for 25ms before timeout occurs. After this time, the slave must be able to receive a new start condition within 35ms.

          b) SHTF2 is for both modes. It indicates that bus is somehow locked and there isn’t possible communication.

          c) I2Cx_SLTH and I2Cx_SLTL registers could be loaded with number of bus clocks = “LoValue” which defines timeout values.

          d) Effectively, any down-up-down or up-down-up transition on the data line that occurs within the number of clock cycles programmed in this register is ignored by the I2C module. The programmer must specify the length of the glitch (in terms of bus clock cycles) for the filter to absorb and not pass. You can set 1-31 bus clock cycles (20-620ns for 50MHz bus clock) and value should be selected on base of noise analysis directly in your system

     3. Unfortunately I do not know about any specific example code directly for this topic. I could recommend AN4771 SMBus Quick Start Guide:    

http://www.freescale.com/files/32bit/doc/app_note/AN4471.pdf

AN4342 Using the Inter-Integrated Circuit on ColdFire+ and Kinetis

http://www.freescale.com/files/analog/doc/app_note/AN4342.pdf

http://www.freescale.com/files/analog/doc/app_note/AN4342.rar

and Freescale Power Management Bus (PMBus) Library

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=PMBUSLIB

I hope it helps you.

Have a great day,
RadekS

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