What the conditions will we use the DDR3 Write Leveling features？we dont know why we need to fix the following Data pin ,in other word, D0 is connected to DRAM_D8 not DRAM_D0.
FSL review command as below:
The review was finished. One comment about DDR3 data swapping of the review,
Hardware write leveling – lowest order bit within byte lane must remain on lowest order bit of lane
by JEDEC compliance (see the “Write Leveling” section in JESD79-3E)
— D0, D8, D16, D24, D32, D40, D48, and D56 are fixed
— Other data lines free to swap within byte lane
For example, DQ0 of U3 should connect to net-label DRAM_D8.