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T4240 reset configuration word

Question asked by eric skullerud on Feb 22, 2015

Can anyone explain how to set up the RCW to activate SRIO @ 3.125G, on PCIe slot #6 (SERDES #3) (OS = VxWorks 6.9.4.3)?

 

I've been studying Sections 4 (resets, CCSR's, clocking, RCW) and 18 (SERDES) T4240 QorIQ Integrated Multicore Communications Processor Family Reference Manual.

 

I see in the RCW definitions in Table 4-54, there are a number of fields that pertain to SRIO configuration. However, most of these that i have identified don't make much sense to me from the limited description.

 

Have been trying to correlate the RCW fields pertaining to SRIO/SD3 with the CCSR's that actually hold this data. But it mapping is not clear at all and have not found any discussion of this in the documentation available to us.

 

Have tried reading and writing config registers for SERDES SD3, to set up the reference clock and otherwise activate SRIO on slot 6.

 

One really fundamental question is whether our understanding of what the base address for SD3 is correct - 0xFE000000 (CCSR base) + 0xC0000 (SRIO) + 0xEC000 (SERDES3)???

 

I have an installer for something called the QVCS, but haven't been successful with the installation so far (onto a Win7 machine), as the install fails.

 

Before I go any further with details, would like  to first ask if there is anyone here who has successfully configured SRIO as I've described above?

If so, I can provide further info about what I see in the documents and what details I'm hung up on.

 

 

Thank you.

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