I'm in the process of developing a minimalist USB audio interface around the SGTL5000 and competition's LPC1347 (clocked at 72 MHz), and I am having a hard time figuring out the best clock configuration. Since MCLK is going to be obtained by integer frequency division, it is likely going to have to be 12 MHz. From what I can tell, this leaves me with three options:
- Using the PLL and having the SGTL as I2S master (inconvenient for several reasons),
- an "odd" sample rate of 46.875 kHz (12000000 Hz / 256, which would be by far my preferred choice), or
- a just as hacky solution with 44.1 kHz LRCLK, 1.5 MHz SCLK, and transmission breaks in between samples.
In order to figure this out, I would appreciate knowing more about how the SGTL internally synchronizes to I2S data - can I, for instance, use a higher SCLK and just wait with the transmission of the next sample until the end of the LRCLK interval? Are there any known cases where such situation has been successfully resolved with the SGTL as I2S slave? What would be the corresponding settings?