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ddr test can't run correctly on hdmi-dongle board.

Question asked by chuanyan yin on Aug 26, 2014
Latest reply on Aug 26, 2014 by igorpadykov

This is very strange,

 

I use ddr test run on sabrelite and on ott tv-box, and my custom board , all these works fine, but when I run ddr test on hdmi-dongle board, I can't pass DQS gating, read/write delay calibration. Why this happened? I have tried ddr test  v1.0.3, the result is same. But when I run u-boot.bin in the board, and run command mtest, the board worksf fine.  Here is the log.

 

D:\DDR_Stress_Tester_V1.0.2\DDR_Stress_Tester_V1.0.2\Binary>DDR_Stress_Tester.ex

e -t mx6x -df scripts\MX6_series_boards\SabreSD\RevC_and_RevB\MX6DQ\MX6Q_SabreSD

_DDR3_register_programming_aid_v1.5.inc

MX6DL opened.

HAB_TYPE: DEVELOP

Image loading...

download Image to IRAM OK

 

 

Re-open MX6x device.

Running DDR test..., press "ESC" key to exit.

 

 

 

 

 

 

 

 

******************************

    DDR Stress Test (1.0.2) for MX6DL

    Build: Dec 10 2013, 12:31:47

    Freescale Semiconductor, Inc.

******************************

 

 

=======DDR configuration==========

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 14, col size: 10

Chip select CSD0 is used

Density per chip select: 1024MB

==================================

 

 

 

 

What ARM core speed would you like to run?

Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz

^C

D:\DDR_Stress_Tester_V1.0.2\DDR_Stress_Tester_V1.0.2\Binary>DDR_Stress_Tester.ex

e -t mx6x -df scripts\MX6_series_boards\SabreSD\RevC_and_RevB\MX6DQ\MX6Q_SabreSD

_DDR3_register_programming_aid_v1.5.inc

MX6DQ opened.

HAB_TYPE: DEVELOP

Image loading...

download Image to IRAM OK

 

 

Re-open MX6x device.

Running DDR test..., press "ESC" key to exit.

 

 

 

 

 

 

 

 

******************************

    DDR Stress Test (1.0.2) for MX6DQ

    Build: Dec 10 2013, 12:31:54

    Freescale Semiconductor, Inc.

******************************

 

 

=======DDR configuration==========

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 14, col size: 10

Chip select CSD0 is used

Density per chip select: 1024MB

==================================

 

 

 

 

What ARM core speed would you like to run?

Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz

  ARM set to 1GHz

 

 

Please select the DDR density per chip select (in bytes) on the board

Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6

for 32MB

For maximum supported density (4GB), we can only access up to 3.75GB.  Type 9 to

select this

  DDR density selected (MB): 1024

 

 

 

 

Calibration will run at DDR frequency 528MHz. Type 'y' to continue.

If you want to run at other DDR frequency. Type 'n'

  DDR Freq: 528 MHz

 

 

Would you like to run the write leveling calibration? (y/n)

  Please enter the MR1 value on the initilization script

  This will be re-programmed into MR1 after write leveling calibration

  Enter as a 4-digit HEX value, example 0004, then hit enter

0004 You have entered: 0x0004

Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x000F000A

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00170017

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x000D001F

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x017F0008

 

 

Would you like to run the DQS gating, read/write delay calibration? (y/n)

Starting DQS gating calibration...

. . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

 

 

The DDR stress test can run with an incrementing frequency or at a static freq

To run at a static freq, simply set the start freq and end freq to the same valu

e

Would you like to run the DDR Stress Test (y/n)?

 

 

Enter desired START freq (135 to 672 MHz), then hit enter.

Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.

528

  The freq you entered was: 528

 

 

Enter desired END freq (135 to 672 MHz), then hit enter.

Make sure this is equal to or greater than start freq

528

  The freq you entered was: 528

 

 

Beginning stress test

 

 

loop: 1

DDR Freq: 528 MHz

t0.1: data is addr test

Address of failure: 0x10000000

Data was: 0x00001000

But pattern  should match address

Outcomes