I'm going through the Reference Manual and finding a lot of obvious errors (apart from the spelling errors).
There doesn't seem to be an Errata or update to this manual.
Is anyone keeping a list of errors, because Freescale doesn't seem to be doing this.
Is there a "place" of some sort on this site where this sort of document could be created, indexed and more importantly FOUND by others using this manual?
Here are ones I've found in the following document over the course of a few days trying to track down a DDR3 memory problem that happens at high and low temperatures.
i.MX53 Multimedia Applications Processor Reference Manual
Document Number: iMX53RM
Rev. 2.1, 06/2012
Table 43-2. DDR Output Driver Average Impedance
DDR3 mode - Calibration resistance = 200
This doesn't match:
43.3.454 IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
NVCC_EMI_DRAM=1.5V+/-5% (DDR3), ddr_sel='00': 240 Ohm
Table 43-2. DDR Output Driver Average Impedance
DDR3 mode: Hi-Z4, 240, 120, 80, 60, 48, 48, 34.
The resistance values listed for "5" and "6" are the same.
I have measured the resistances on the DDR_RESET pin as
approximately "246, 108, 71, 53, 43, 35, 30" indicating
that the duplicates in the table are a a mistake. The
equivalent tables in the i.MX6 manuals give 240, 120,
80, 60, 48, 40 and 34 ohms.
43.3.343 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
43.3.347 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
43.3.352 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
43.3.357 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
Both the Diagram and Table state that the 22:24 field is
"Reserved and Read Only" when it has to be written with
the ODT value, as these pins are I/O (as are the data pins).
Checking the registers in the debugger shows these bits to be
read/write and the Freescale sample code sets these bits.
The Diagram also shows the Reset state as "1" wuile the
Description shows it as "0".
43.3.353 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
43.3.346 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
The SDODT0 register diagram has the ODT field read/write whereas
the description has it read-only, and the register is read-only.
The SDODT1 section is correct.
43.3.344 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1
43.3.356 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0
The register diagram has the DSE field read/write whereas the
description has it read-only, and the register is read-only.
43.3.359 IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ
43.3.360 IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ
The Register Diagram gives the Reset State of the DSE_TEST and PUE
bits as "1" while the description has them as "0". The "Strength Mode"
bit is the reverse,"0" in the Diagram and "1" in the Description.
43.3.358 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
The Diagram shows the PUE reset value of "1" and the PUS reset
value of "00" whereas the text shows PUS as "0" and PUS as "10".
The DQM0, DQM2 and DQM3 sections are correct.
43.3.278 IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO
The Diagram gives DSE and SRE as read-only while the Description
has them as read-write.
43.3.351 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
The Diagram gives PKE, PUE and PUS as read-write whereas the
Description has them as read-only. The SDCLK_1 section is OK.
In Addemdum 2:
Table 2-10. Common Fusemap
Address 0C00 is shown to be in Bank 0 when it is in Bank 1. This
is correct in section 2.2.
2.2 Fusemap Description Table
Addresses 1814, 1818 and 181C are shown to be in Bank 0. This
is correct in Table 2-10.
Tom