SPI CS active through a write and read cycle?

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SPI CS active through a write and read cycle?

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marknordstrand
Contributor III

MK20DN512VLQ10 with CW 10.4. 

 

Connected to flash which needs CS asserted through the command, address (both writes), and the reading of the data.  I don't see a way to do this with SPIMaster_LDD short of taking over CS as a GPIO and controlling it directly.  Is this correct, or am I missing something?

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ZhangJennie
NXP TechSupport
NXP TechSupport

hello Mark:

There are some issues with the PE SPI driver (not really bugs, but deficiencies). You can find workarounds and more details in the next thread from the Freescale community:

https://community.freescale.com/thread/307520

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Best Regards,

ZhangJun

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