SPI CS active through a write and read cycle?

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

SPI CS active through a write and read cycle?

728 次查看
marknordstrand
Contributor III

MK20DN512VLQ10 with CW 10.4. 

 

Connected to flash which needs CS asserted through the command, address (both writes), and the reading of the data.  I don't see a way to do this with SPIMaster_LDD short of taking over CS as a GPIO and controlling it directly.  Is this correct, or am I missing something?

标签 (1)
0 项奖励
1 回复

555 次查看
ZhangJennie
NXP TechSupport
NXP TechSupport

hello Mark:

There are some issues with the PE SPI driver (not really bugs, but deficiencies). You can find workarounds and more details in the next thread from the Freescale community:

https://community.freescale.com/thread/307520

==================================

this answer is for you. if it helps, please click on "correct answer" button. thanks!

Best Regards,

ZhangJun

0 项奖励