1. Is the POR reset bit in the RCM_SRS0 register only set on a VDD POR? Are there any other instances that will set this bit?
2. If the VDD POR were to occur while the K61 is in VLLS2, will the chip wake up via a reset?
- Customer uses two MK61FN1M0CAA12's running in lockstep in their design. They use an external osc divided down to a 50Mhz core and bus clock. and approx a 20Mhz Flexbus and Flash clock.
- They use one supply source of 1.8v to supply power to VDD and VBAT to both chips.
- The chip will boot up to full run mode, and after sensing inactivity will transition to VLPR mode. Upon an interrupt or command the chip will transition back to RUN mode and handle the interrupt or command,
- If main power is removed the code will transition to K61 to VLLS2 mode. There is a 1.8v "Hold Up Battery" to keep voltage to the chip when main power is removed.
- There are various low level wakeups enabled while the chips are in VLLS2 mode. We have DRYICE enabled for Pin and Voltage tamper.
- We use the 32 byte VBAT ad SYSTEM registers to store data. If a POR happens we expect the data stored in these locations to be invalid.
KEY ASPECT: On a POR we expect DRYICE to remove data in VBAT register only. For this reason we use the POR bit in the RCM_SRS0 register to indicate that a VDD POR bas occurred. If we see that this bit is set we will initialize the VBAT and SYSTEM registers. However we are seeing intermittent POP occurences, which impact our board's proper operation.