It is the question about the sequence of the SelfRefresh cancellation of LPDDR2.
・I set follows at the time of LPSTOP3 transition.
②SelfRefresh of LPDDR2 setting.
・I set follows after LPSTOP3 return.
①Setting of IOMUX,ANADIG,CCM
②Setting of DDRMC
③Cancellation of SelfRefresh of LPDDR2.
When I carry out SelfRefresh cancellation of LPDDR2, is the following setting all right?
DDRMC->CR35 = DDRMC_CR35_LP_CMD(0x1); // = Exit specified state, (exit low power mode)
Is the confirmation of the status of the SelfRefresh cancellation necessary?