AnsweredAssumed Answered

about sequence of the SelfRefresh cancellation of LPDDR2

Question asked by Soichi Yamamoto on Jan 29, 2014
Latest reply on Mar 4, 2014 by Naoum Gitnik

Hi

 

It is the question about the sequence of the SelfRefresh cancellation of LPDDR2.


・I set follows at the time of LPSTOP3 transition.

 ①SRC_MISC2_0=1 setting.

 ②SelfRefresh of LPDDR2 setting.

 ③LPSTOP3 setting

 

・I set follows after LPSTOP3 return.

 ①Setting of IOMUX,ANADIG,CCM

 ②Setting of DDRMC

 ③Cancellation of SelfRefresh of LPDDR2.

 

Q1)

When I carry out SelfRefresh cancellation of LPDDR2, is the following setting all right?

DDRMC->CR35 = DDRMC_CR35_LP_CMD(0x1);       //[0] = Exit specified state, (exit low power mode)


Q2)

Is the confirmation of the status of the SelfRefresh cancellation necessary?

 

Best Regards,

soichi

 


Outcomes