about sequence of the SelfRefresh cancellation of LPDDR2

[soichiyamamoto]

Hi

It is the question about the sequence of the SelfRefresh cancellation of LPDDR2.

・I set follows at the time of LPSTOP3 transition.

　①SRC_MISC2_0＝１ setting.

　②SelfRefresh of LPDDR2 setting.

　③LPSTOP3 setting

・I set follows after LPSTOP3 return.

　①Setting of IOMUX,ANADIG,CCM

　②Setting of DDRMC

　③Cancellation of SelfRefresh of LPDDR2.

Q1)

When I carry out SelfRefresh cancellation of LPDDR2, is the following setting all right?

DDRMC->CR35 = DDRMC_CR35_LP_CMD(0x1);       //[0] = Exit specified state, (exit low power mode)

Q2）

Is the confirmation of the status of the SelfRefresh cancellation necessary?

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

Please, turn to our local FAE, who might be able to provide you with the code potentially helping you - code for DDR (on the DDR3 example) self-refresh when Vybrid in LPStop.

It is posted in the internal Community thread Re: Vybrid Low Power Options - AN Feedback Requested.

Sincerely, Naoum Gitnik.

[soichiyamamoto]

Dear Naoum,

Thank you for reply.

I add a question.
Please give me an answer.

Q1). The setting of DDRMC_CR35_LP_CMD(0x1) is not included in a source code, but is it necessary to set it to cancel self-refreshment with holding data?

Q2)  After LPSTOP3 cancellation, the phenomenon that a part of the data of LPDDDR2 fails is confirmed, but is there the probable cause?

Best regards,

soichi

[rendy · Accepted solution]

Q1). The setting of DDRMC_CR35_LP_CMD(0x1) is not included in a source code, but is it necessary to set it to cancel self-refreshment with holding data?

Actually this setting is included in the source code (if we are talking about 'low_power_ddr' example). It's in function 'void exit_ddr_self_refresh(void)' in file 'low_power_ddr.c'.

[soichiyamamoto]

Dear Rene,

Thank you.That's right!

I will test this setting.

Best Regards,

Soichi

[soichiyamamoto]

Dear Naoum,

I apologize for the delay in notifying you.

In EXIT of LPSTOP3, I confirmed that I could correct movement of self_refresh exit of LPDDR2.

In self_refresh exit of LPDDR2, the following processing reaches.

  DDRMC->CR35 = DDRMC_CR35_LP_CMD(0x1);

-------------------------------------------------------

I have a question.

It is a rare case, When I leave LPSTOP2, MCU may be hung up.

State at the time of the hangup

　・BCTRL signal changes in Low → Hi.

　・Exit handling of including the setting GPIO is completed.

　・CKE of the DDR is a state of L

I seem to be hung up in SelfRefresh EXIT.

Q1）Should I do WAIT after the following processing?

If I do WAIT, Which time is suitable?

  DDRMC->CR35 = DDRMC_CR35_LP_CMD(0x1);

Q2）Please give me advice to be settled.

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

I might not understand the question properly, but you are probably asking if you are waiting long enough for the LPDDR2 chip to exit the Self-Refresh mode?

If this is what you mean, quite likely you are right.

For how long to wait? - You may either look in the LPDDR2 datasheet how long it takes the command to execute or just define the 'wait' duration empirically and after that, to be on the safe side, verify it in the LPDDR2 datasheet.

The fact that it only happens rarely means that your code is quite close to proper behavior.

Regards, Naoum Gitnik.

rendy

[soichiyamamoto]

Dear Naoum,

Thank you for fast reply.

Your understanding is right.

In the waiting time, is the following information of the data sheet of LPDDR2 all right?

　　・SelfRefresh exit to next valid command delay

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

IMO, this is the delay ("Self-Refresh exit"-to-"next valid command" delay) you have to look for in the datasheet of LPDDR2 you are using.

(Frankly, I tried to quickly find it in the LPDDR2 datasheet you provided earlier but got lost (sorry...); the best way would be turning to their Support with this question.)

Regards, Naoum Gitnik.

[soichiyamamoto]

Dear Naoum,

Thank you for reply.

We settled this matter.（hung up）

Thank you very much for giving me many advice.

I have question.

In specific Board, time before calling PERSISTENT_ENTRY0 from LPSTOP3 Exit is long, And it does not rise frequently.

When it is long, these are more than 500ms.

Q）Why is it to become that time to call PERSISTENT_ENTRY0 from LPSTOP3 Exit is long?

Q)Please give me the advice.

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

I am glad the Self-Refresh EXIT issue is resolved.

Regarding the LPSTOP3 Exit related 500ms delay - do you mean it is that long only on your board but not when you use our, e.g. Tower, board? - In this case, it makes sense to look at the differences between the 2 designs...

Hopefully, based on your answer, Rene Kolarik, who had been already taking care of SW in this thread, will be able to comment.

Regards, Naoum Gitnik.

[soichiyamamoto]

Dear Naoum,

I'm sorry.

I misunderstood.

I withdraw this question(LPSTOP3 Exit related 500ms delay).

And I ask this question again.

Test results

The problem is time of ,②.

Only a specific apparatus has a long section of ②.

Time polling the CR80 status of the DDR controller after the initialization for DDR is very long.

I poll this bit (Bit [8] = The MC initialization has been completed.).

Q1)

Can you think of any reasons?

Q2)

Is the setting of SRC_MISC2[MISC2_0] related?

Q3)

Please give me advice as to what I should do from now on.

Best regards,

soichi

[naoumgitnik]

Dear Soichi,

Is there any correlation between the section ② duration and how long it takes the 24MHz crystal oscillator to wake up on each of these 3 boards?

May you at the same time also monitor the BCTRL pin voltage, please? Any correlation either?

Regards, Naoum Gitnik.

rendy

Update from https://community.freescale.com/message/387671?et=watches.email.thread#387671 thread:

"To improve 24MHz clock quality, they changed 24MHz source from crystal unit to crystal oscillator, then delayed CKE issue was improved."

/N.G.

[naoumgitnik]

Dear Soichi,

A2.

Quite likely it is not the Vybrid code but rather the fact that the DDR chip does not stay in the Self-Refresh mode after Vybrid switches into LPStop and its IOs become High-Impedance.

I know DDR3 chip used on our Tower board needs a pull-up on the DDR_RST line and pull-down on the DDR_CKE line.

Plewase, take a look at your LPDDR2 datasheet to see what DDR control lines are involved in Self-Refresh and apply the same approach accordingly.

A1.

rendy, may you take a look at the referred code and answer this SW-related question, please?

Sincerely, Naoum Gitnik.

[soichiyamamoto]

Drea  Naoum,

thank you for reply.

About A2.

DDR_CKE　is 100KΩ pulldown.

I attach LPDDR2 datasheet which I use.

Is there not some necessary thing by a sequence of SelfRefresh?

Best Regards

soichi

[naoumgitnik]

Dear Soichi,

A2.

Based on the 6.4.17 section of the provided LPDDR2 datsahseet, CKE indeed needs to stay low in the self-refresh mode, and all the other signals are  "don't care".

You may try something lower than 100K to be on the safe side, e.g. 10K, but I doubt that the problem is with the CKE signal.

A1.

rendy, may you take a look at the referred code and answer the question, please?

Sincerely, Naoum Gitnik.

[rendy]

Ok, I'll look at it and consult it with Jiri Kotzian.

[soichiyamamoto]

Dear Naoum,

about A2.

I looked about CKE signal.
After SelfRefresh mode shift, it is CKE Low. And being CKE High after SelfRefresh mode cancellation.　And I confirmed it with an oscilloscope.
If there is the point that you should confirm elsewhere, please tell me.

Best Regards,

soichi