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I2C0 scl & I2c1 scl to be configured for 400khz in I.MX28 BSP for I.MX28 EVK

Question asked by srinivasan shanmugam on Sep 29, 2013
Latest reply on Oct 13, 2013 by Serhii Dolzhenko

Dear All,

 

 

I need to configure I2C0 SCL& I2C1 SCL to 400khz could you anybody please kindly how this can be done  in I.MX28 BSP & verified in I.MX28 EVK, as I was unable to figure it out how to configure it to 400khz in I.MX28 BSP

 

I found out few information but it didn't help me,

 

In regs-i2c.h in linux/arch/arm/mach-imx28

 

#define BP_I2C_TIMING0_HIGH_COUNT       16

 

and compared with description from sect.27.5.2 "I2C Timing Register 0

(HW_I2C_TIMING0)" i.MX28 Reference Manual (rev.1, 9/2010):

 

"HW_I2C_TIMING0_WR(0x000F0007); // high time = 15 clocks, read bit at

7 for 400KHz at 24mhz"

 

<http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf>

 

But " BP_I2C_TIMING0_HIGH_COUNT " is not used in the I2c bus driver or I2c chip driver as it is only defined in the regs-i2c.h & more over the entire regs-i2c.h is being protected under the flag "#ifndef __ARCH_ARM___I2C_H" , could any body pls let me know how this is getting invoked in my I2c bus driver or i2c chip driver

 

Could you please let me know the  how i2c scl frequency is configured for 400khz for I2c0 bus & I2c1 bus & how this is getting invoked in the i2c driver code

 

as it is neither being invoked in the following files

 

drivers/i2c/busses/i2c-mxs.c

drivers/i2c/busses/i2c-mxs.h

arch/arm/mach-mx28/include/mach/regs-i2c.h

#define BP_I2C_TIMING0_HIGH_COUNT       16

 

and compared with description from sect.27.5.2 "I2C Timing Register 0

(HW_I2C_TIMING0)" i.MX28 Reference Manual (rev.1, 9/2010):

 

"HW_I2C_TIMING0_WR(0x000F0007); // high time = 15 clocks, read bit at

7 for 400KHz at 24mhz"


Kindly do the needful, as am stuck with this for many days, any help would be greatly appreciated

Thanks in advance,



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