I found an inconsistency in Vybrid Reference Manual Rev. 5 07/2013 in chapter 11.21.27 ANADIG PLL Lock register (ANADIG_PLL_LOCK) , where the field and the description aren't matching. E.g. field 6 PLL1, where the description says PLL7 is locked or not locked. I just wanted to inform You and I'm not sure if I'm right at this community place.
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