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Correct setup of the K10 Internal Reference Clock...

Question asked by Alex Thompson on Jul 23, 2013
Latest reply on Sep 1, 2013 by Hui_Ma

We're trying to get the full 72MHz system clock out of a 64-pin, 72MHz K10. We've pulled code in from PE, setting the DCO up to give us 2197x32.768=71.99MHz. After setting up a UART and noticing some bad characters, I checked the bit period on a scope and found that it was off by 2.9% (after taking the baud rate error created by the UART divisor into account).

 

So, my question is - should the FLL output, using the IRC, be able to produce a reliable 72MHz?

 

Here's the setup code from PE:

void __init_hardware()

{

  /*** PE initialization code after reset ***/

  SCB_VTOR = (uint32_t)__vector_table; /* Set the interrupt vector table position */

  /* Disable the WDOG module */

  /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */

  WDOG_UNLOCK = (uint16_t)0xC520U;     /* Key 1 */

  /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */

  WDOG_UNLOCK  = (uint16_t)0xD928U;    /* Key 2 */

  /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */

  WDOG_STCTRLH = (uint16_t)0x01D2U;                 

  /* System clock initialization */

  /* SIM_SCGC5: PORTA=1 */

  SIM_SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */

  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  SIM_CLKDIV1 = (uint32_t)0x01330000UL; /* Update system prescalers */

  /* SIM_SOPT2: PLLFLLSEL=0 */

  SIM_SOPT2 &= (uint32_t)~0x00010000UL; /* Select FLL as a clock source for various peripherals */

  /* SIM_SOPT1: OSC32KSEL=0 */

  SIM_SOPT1 &= (uint32_t)~0x000C0000UL; /* System oscillator drives 32 kHz clock for various peripherals */

  /* Switch to FEI Mode */

  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */

  MCG_C1 = (uint8_t)0x06U;                            

  /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */

  MCG_C2 = (uint8_t)0x00U;                            

  /* MCG_C4: DMX32=1,DRST_DRS=2 */

  MCG_C4 = (uint8_t)((MCG_C4 & (uint8_t)~(uint8_t)0x20U) | (uint8_t)0xC0U);

  /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

  OSC_CR = (uint8_t)0x80U;

  /* MCG_C7: OSCSEL=0 */

  MCG_C7 &= (uint8_t)~(uint8_t)0x01U;                          

  /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */

  MCG_C5 = (uint8_t)0x00U;                            

  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */

  MCG_C6 = (uint8_t)0x00U;                            

  while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */

  }

  while((MCG_S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */

  }

  /*** End of PE initialization code after reset ***/

}

 

Cheers.

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