Hello - I am about to dive into implementing a custom embedded design with the i.MX6Q. To help accelerate the design process, I am reviewing the schematic, BOM, and PCB layout files that are provided with the SABRE-SDB. After just a very brief review of the 8-layer PCB stack-up and routing, it is readily apparent that this PCB layout is problematic and falls well short of my expectations for design work from Freescale. The PCB layout provided does not meet the routing guidelines specified in the Freescale IMX6DQ6SDLHDG Hardware Development Guide (Section 2.5.8): "High speed signals (DDR,..) must not cross gaps in the reference plane. Avoid creating slots, voids, and splits in reference planes. Review via voids to ensure they do not create splits (space out vias)".
The 8-layer stack-up deployed has numerous cuts / moats in the (2) DC power planes (layers 4 & 5). These cuts are to be expected - but must be avoided by trace routing. Based on the dielectric thicknesses called out in the .DSN file, the asymmetric stripline routing (layers 3 & 6) will image ~40% of their return current onto these cut-up power planes (and ~60% onto the continuous GND planes (layers 2 and 7). Please comment on how it is OK for this layout to ignore both industry best practice and the IMX6DQ6SDLHDG HW Dev Guide which specify that high speed traces must reference only continuous planes.
Given the extent to which design teams take reference platform schematics and PCB layouts as verbatim, then I think it is critical to openly discuss potential design performance shortcomings. Has any EMI emissions testing been performed on this PCBA? If yes, can the results be posted?