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Dual-Channel LPDDR2 Routing Rules for i.MX6

Question asked by David Roach on Apr 19, 2013
Latest reply on Apr 21, 2015 by Frank Ambrosious
Branched to a new discussion

In a dual-channel LPDDR2 memory design for i.MX6, is it necessary for all four clock signals of the two channels to be the same length +-5mils?  Or can each channel's clocks be different lengths as long as the two signals of each differential pair are matched to within +-5mils?

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