Dual-Channel LPDDR2 Routing Rules for i.MX6

[davidroach]

In a dual-channel LPDDR2 memory design for i.MX6, is it necessary for all four clock signals of the two channels to be the same length +-5mils?  Or can each channel's clocks be different lengths as long as the two signals of each differential pair are matched to within +-5mils?

[petergabor]

Hi,

we are considering to use  dual channel LPDDR2 too, could you send us your LPDDR2 schematics for the reference. Thank you.

[davidroach]

Sorry, Peter, corporate policy does not allow me to share our schematics.  However, the Freescale reference design for i.MX6 LPDDR2 has been shared in another forum thread and is available here:

https://community.freescale.com/servlet/JiveServlet/download/400503-274431/arik_lpddr2_06_16_2011.pd...

That is the same design I based ours on.

Regards,

Dave

[frankambrosius]

Hello Dave and others,

I'm looking for adding a dual rank/dual channel LPDDR2 to an i.MX6 Dual Lite.

Is the reference design also valid for my case? Is a layout of this reference design available?

Thank you for your help.

Regards,

Frank

[rp123]

Would you be able to provide your DCD settings used to initialize lpddr2 on the imx6dq?  I am having trouble writing to ddr2 from jtag, i am receiving a pattern of alternating FFFFFFFFF's and 00000000's

[Yogee]

HI,

I also have some doubts on LPDDR2 interface with IMX6 solo. Whether bit swapping within byte is allowed sicne JEDEC std does not mentioned about this.

Yogee

[davidroach · Accepted solution]

For the benefit of the rest of the community, I did send Jimmy our LPDDR2 schematic page.  The configuration is two Micron 128Mx32 LPDDR2 chips in a dual-channel interleaved 1GB, 64-bit wide memory system.  Jimmy's reply after verification with his engineers was that yes indeed, the clock lines can be different lengths between the two channels.  Only the signals within a given channel need be matched according to the routing rules in the design guideline.  Each channel can be routed independently without regard to the other channel.

[jimmychan]

Please download this IMX6DQ6SDLHDG. Section 2.4 talk about this.

[davidroach]

That document gives very specific rules for routing single-channel DDR3 signals.  Table 2-3 specifies to match DRAM_SDCLK[1:0] and DRAM_SDCLK_B[1:0] within +-5mils.  I can understand that all the clocks must be delay-matched in a single channel memory array.  DDR3 can only be used in single-channel memory configurations on the i.MX6.

My question relates to the dual-channel LPDDR2 configuration on the i.MX6 which operates with two independent DDR control blocks.  In that case, the differential pair DRAM_SDCLK[0] and DRAM_SDCLK_B[0] are driven by one controller and must be matched to each other within +-5mils.  The other DDR controller drives DRAM_SDCLK[1] and DRAM_SDCLK_B[1] and they must also be matched to each other within +-5mils.

The question is this:  Does the differential signal pair SDCLK[0] need to be the same length as the differential pair SDCLK[1]?  There are no LPDDR2 signals that are common to the two clock domains, so it would seem that the two channels could have different clock lengths.  Section 2.4 of IMX6DQSDLHDG does not directly address this question.

[jimmychan]

Would you send me the part of your LPDDR2 schematic? our hardware engineer want to check it first and then give you more accurate answer. Thanks.

If you don't want to put it on this public community, please send to my email : jimmy.chan@freescale.com