IMX6 DI CLOCK IN UBOOT

[jianminlv]

Hi, all

IMX6RM said DI clock can be derived from HSP_CLK or from an external source(via the ipp_di_#_ext_clk pin), and configured by DI#_CLK_EXT bit of IPUx_DIx_GENERAL.Some related configuration in u-boot:

lvdev_num=1(di = 1) set in envirenment.

CCM_CCGR3:

location:board/freescale/mx6_sabresd/mx6_sabresd.c:

        reg |= 0xC033;

        writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3)

which will select ipu1_ipu_clk_enable\ipu1_ipu_di1_clk_enable\ldb_di1_clk_enable

IPUx_DI1_GENERAL:

bit20 = 1(indecates external clk)

location:board/freescale/mx6_sabresd/mx6_sabresd.c:

ipuv3_fb_init(&lvds_xga, di,IPU_PIX_FMT_RGB666,DI_PCLK_LDB, 65000000);

CCM_CS2CDR:

location:location:board/freescale/mx6_sabresd/mx6_sabresd.c:

    reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);

    reg &= ~0x00007E00;

    reg |= 0x00003600;

    writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);

which will select MMDC_CH1 clock for ldb_di0_clk and ldb_di1_clk

CCM_CSCMR2:

location:location:board/freescale/mx6_sabresd/mx6_sabresd.c:

    reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);

    reg |= 0x00000C00;

    writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);

Control for divider of ldb clock for IPU di1 to 7

CCM_CHSCCDR:

location:location:board/freescale/mx6_sabresd/mx6_sabresd.c:

    reg = 0x0002A953;

    writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);

Selector for ipu1 di1 root clock multiplexer: derive clock from ldb_di1_clk

CCM_CBCMR\CCM_CBCDR were not configured in u-boot(I did not find any location to write them)

According to above analyzation, I get following conclusion:

PPL2(528)->/1->MMDC_CH1_CLK_ROOT->/7->LDB_DI_CLK->DI CLK

di clk=PPL2 528 / 7 = 75.4 MHz

!!!BUT!!! sabresd's LCD pixel clk need 65MHz, can somebody help me to explain it?

Then IPU_PM :

location:location:drivers/video/ipu_disp.c

    ipu_init_sync_panel:

    /* Enable for a divide by 2 clock change. */

    reg = __raw_readl(IPU_PM);

    reg &= ~(0x7f << 7);

    reg |= 0x20 << 7;

    reg &= ~(0x7f << 23);

    reg |= 0x20 << 23;

    __raw_writel(reg, IPU_PM);

di clk = Fast_freq / 2, meaning 75.4/2= 37.7 ??

IPUx_DI1_BS_CLKGEN0:

location:location:drivers/video/ipu_common.c

ipu_pixel_clk_set_rate:

11–0:di1_disp_clk_period

"DI1 Display Clock Period. This field defines the Display interface clock period for display write access. This parameter contains an

integer part (bits 11:4) and a fractional part (bits 3:0). It defines a fractional division ratio of the HSP_CLK

clock for generation of the display's interface clock."

Does not the di clk come from externel clk? Why does set devider from HSP_CLK here !!

[maheshmahadeva1 · Accepted solution]

Hi.

I would suggest you download the latest release 4.0 release from the below link and use the u-boot code from that release:

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6D&fpsp=1&tab=Design_Tools_Tab

Best regards,

-Mahesh

[jianminlv]

Ok，thanks，I will try it！

[maheshmahadeva1]

Below is the calculation for the IPU1 DI0 clock from the u-boot that was included in the L3.0.35_3.0.0_ER_SOURCE release.

1. IPU1 DI0 is configured to use ldb_di0_clk based on the setting in the CCM_CHSCCDR register at offset 0x34 (bits 0-2)

MX6SDL SABRESD U-Boot > md 20C4034 1

020c4034: 0002a953

2. LDB_DI0 clock is configured to use PLL2 PFD0 as its parent clock based on the setting in the CCM_CS2CDR register at offset 0x2C (bits 9-11) 

MX6SDL SABRESD U-Boot > md 20C402c 1

020c402c: 007212c1

3. LDB DI0 clock divider is set to 7 based on the setting in the CCM_CSCMR2 register at offset 0x20 (bit 10)

MX6SDL SABRESD U-Boot > md 20C4020 1

020c4020: 02b92f06

4. The PLL PFD0 is set to 452MHz based on the setting in the register CCM_ANALOG_PFD_528n at 20C8100. PFD0 is available at bits 0-5 which is set to 21. So 528*18/21=452MHz

MX6SDL SABRESD U-Boot > md 20C8100 1

020c8100: 50185215

Therefore the IPU1 DI0 clock is 452/7=64.65

Best regards,

-Mahesh

[jianminlv]

Hi,Mahesh

Thanks for your reply!

In my uboot source code, CCM_CS2CDR is configured in board/freescale/mx6_sabresd/mx6_sabresd.c:

;;;;;

    reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);

    reg &= ~0x00007E00;

    reg |= 0x00003600;

    writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);

;;;;;

which will select MMDC_CH1 clock for ldb_di0_clk and ldb_di1_clk.

And I got the register value is 007236c1:

MX6SDL SABRESD U-Boot > md 20C402c 1

020c402c: 007236c1

which is different from that you gave.