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IMX6 DI CLOCK IN UBOOT

Question asked by jianmin lv on Mar 15, 2013
Latest reply on May 16, 2013 by jianmin lv

Hi, all

IMX6RM said DI clock can be derived from HSP_CLK or from an external source(via the ipp_di_#_ext_clk pin), and configured by DI#_CLK_EXT bit of IPUx_DIx_GENERAL.Some related configuration in u-boot:

 

lvdev_num=1(di = 1) set in envirenment.

 

CCM_CCGR3:

location:board/freescale/mx6_sabresd/mx6_sabresd.c:

        reg |= 0xC033;

        writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3)

which will select ipu1_ipu_clk_enable\ipu1_ipu_di1_clk_enable\ldb_di1_clk_enable

 

IPUx_DI1_GENERAL:

bit20 = 1(indecates external clk)

 

location:board/freescale/mx6_sabresd/mx6_sabresd.c:

ipuv3_fb_init(&lvds_xga, di,IPU_PIX_FMT_RGB666,DI_PCLK_LDB, 65000000);

 

CCM_CS2CDR:

location:location:board/freescale/mx6_sabresd/mx6_sabresd.c:

    reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);

    reg &= ~0x00007E00;

    reg |= 0x00003600;

    writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);

which will select MMDC_CH1 clock for ldb_di0_clk and ldb_di1_clk

 

CCM_CSCMR2:

location:location:board/freescale/mx6_sabresd/mx6_sabresd.c:

    reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);

    reg |= 0x00000C00;

    writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);

Control for divider of ldb clock for IPU di1 to 7

 

CCM_CHSCCDR:

location:location:board/freescale/mx6_sabresd/mx6_sabresd.c:

    reg = 0x0002A953;

    writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);

Selector for ipu1 di1 root clock multiplexer: derive clock from ldb_di1_clk

 

CCM_CBCMR\CCM_CBCDR were not configured in u-boot(I did not find any location to write them)

 

According to above analyzation, I get following conclusion:

PPL2(528)->/1->MMDC_CH1_CLK_ROOT->/7->LDB_DI_CLK->DI CLK

di clk=PPL2 528 / 7 = 75.4 MHz

 

!!!BUT!!! sabresd's LCD pixel clk need 65MHz, can somebody help me to explain it?

 

Then IPU_PM :

location:location:drivers/video/ipu_disp.c

    ipu_init_sync_panel:

    /* Enable for a divide by 2 clock change. */

    reg = __raw_readl(IPU_PM);

    reg &= ~(0x7f << 7);

    reg |= 0x20 << 7;

    reg &= ~(0x7f << 23);

    reg |= 0x20 << 23;

    __raw_writel(reg, IPU_PM);

 

di clk = Fast_freq / 2, meaning 75.4/2= 37.7 ??

 

IPUx_DI1_BS_CLKGEN0:

location:location:drivers/video/ipu_common.c

ipu_pixel_clk_set_rate:

 

11–0:di1_disp_clk_period

 

"DI1 Display Clock Period. This field defines the Display interface clock period for display write access. This parameter contains an

integer part (bits 11:4) and a fractional part (bits 3:0). It defines a fractional division ratio of the HSP_CLK

clock for generation of the display's interface clock."

Does not the di clk come from externel clk? Why does set devider from HSP_CLK here !!

 


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