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DDR3 FLY BY TOPOLOGY

Question asked by raghavendra anjanappa on Feb 27, 2013
Latest reply on Mar 5, 2013 by Jerry Fan
Branched to a new discussion

IMX6 processor with fly by topology routing meets the timing wrt to the JEDEC specification but the voltage levels are less than 1V where it is suppose to be 1.5V please suggest solution for this rest of the data links seems to be fine.

 

 

i have attached a image of the topology and the waveforms.

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