DDR3 FLY BY TOPOLOGY

[raghavendraanja]

IMX6 processor with fly by topology routing meets the timing wrt to the JEDEC specification but the voltage levels are less than 1V where it is suppose to be 1.5V please suggest solution for this rest of the data links seems to be fine.

i have attached a image of the topology and the waveforms.

[JerryFan · Accepted solution]

1. Per the topology.jpg, the Rt was pull down to the GND, while I think it should be pull up to DDR_VTT(0.75V) and connected to GND with a capacitor. Please refer i.mx6dq CPU board schematic.

2. I don't know the simulation and ISIB model. But for i.mx6dq DDR pad, the drive strength can be configured.What drive strength you are using? Try other value if you can.