Root cause finally investigated, and a formal bug report (DDTS ENGcm12376 ) opened to i.mx51.
Errata should be updated accordingly. Not sure what are the i.mx51 SoC team schedule for that.
For your convenince, here is the "description" section of the of the bug report:
DDR2 JEDEC standard requires the DDR clock, SDCLK, to start toggling
at least 200uS before clock enable ,SDCKE, signal rise.
In ESDCTLv2 IP implementation, it is implemented by counting 7 CKIL
clock periods , which are 30.3uS*7>200uS
In practice, SDCKE wait period can be as short as 6 CKIL periods, thus
violating the above JEDEC requirement.
Root cause of this are actually 2 design issues:
1. ESDCTL actually counts CKIL half cycles. half cycle conter
(sdctl_core/wack_counter[4:0]) counts from 0 to 14. CKIL monitoring
can possibly start very short before CKIL edge, and it is always
terminates few fast clk cycles after the 14th CKIL edge. This way,
only 13 half-cycles are actually counted.
2. In addition, if CKIL monitoring is started during a hi level of
CKIL, the CKIL edge monitoring logic (ref_sequencer/ckil32_edge)
triggers a false CKIL edge signal
When these two combines, ESDCTLv2 actually counts 12 halfs of CKIL ,
which cause the violation.