5208 - using flex bus c/s as address lines

[Dec]

Hi,

I'm using the MCF5208 processor configured for 32 bit data bus.

I need to address a device which has a 64MB address space which I intend to do by using one of the FBCS lines as the actual device chip select and two further FBCS lines programmed to overlap in such a way that they simulate address lines A24 and A25.

The device I need to address is 32 bits.

Has anyone done this before and is there anything I should be aware of ?

In the datasheet is the statement -

"Should an address match multiple CSARs, the matching chip select signals are driven; however, the chip select signals are driven during an external burst-inhibited bus cycle with external termination on a 32-bit port."

I am using external termination, but what does the above statement actually mean ?

Although my device is 32bits are byte and word accesses still OK in this mode ?

Any help much appreciated.

Thanks

[melissa_hunter]

Since you have your memory setup for a 32-bit port using external termination, then the overlapping chip selects should work for you. You'll still be able to perform byte and word accesses.

As a second possibility, the FlexBus was originally designed as a multiplexed bus. As a side effect of this, the full 32-bit address is actually driven out on the data lines during the first clock of any access. So you could setup an address latch to grab the full 32-bit address from the data lines and use that to address larger memories.

Just wanted to throw the option out there in case you would like to get even more address lines (or if you want some of your chip selects back).

-Melissa

[Dec]

Hi Again,

Just been thinking about the address being driven onto the databus.

If this isn't an official feature of the chip what are the chances of it being removed in later revisions ?

I'm a little concerned about using a feature which doesn't seem to be covered in any docs.

When it comes to latching the address from the data bus how would I do that ?

Would I use the first rising edge of the clock after TS is asserted so that I know I'm in the first cycle ?

Thanks for your help.  Very much appreciated.

[melissa_hunter]

It won't be removed. In fact, we are working on adding this feature into the documentation.

As for latching the address, you would want to use /TS as the enable for a latch. So you latch the address while the /TS signal is low.

[Dec]

Melissa,

Being able to get full access to the missing address lines could be very useful in a future project.

Many thanks for that tip.