i.MX RT1050 RMII Reference Clock

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i.MX RT1050 RMII Reference Clock

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pb1
Contributor I

Hi,

According  to the i.MX RT1050 Processor Reference Manual, Rev. 2, the signal ENET_REF_CLK (on pad GPIO_B1_10) is an input in RMII mode. See Table 40-2. ENET External Signals.

Looking at the IMXRT1050-EVKB schematics, however, this signal seems to be an output from the processor, signal name ENET_TX_CLK, which is used to clock the PHY.

Can anybody please explain this apparent difference in documented signal direction.

Thanks for your help,

Pete Baston.

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miduo
NXP Employee
NXP Employee

Hello,

 Well, here I know it is really confused. Please be note that both ENET_REF_CLK and ENET_TX_CLK are inputs to the pins you route them to by default. This had been clearly indicated in the Reference manual.

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While, it is yes that for IMXRT1050-EVKB, ENET_TX_CLK  is used to clock the PHY. This had been done by software.

By configure ENET PLL(Set ENET1_CLK_SEL to 0 to have the ENET1 TX clock driven by the internal ref_enetpll) and set ENET1_TX_CLK_DIR  to 1 to enable ENET1_TX_CLK output driver that will redirect the generated clock to the PHY.

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pb1
Contributor I

Hi Fang,

Thanks for your reply. So, by configuring  these bits in software we have the choice of two modes, with the 50MHz reference clock being either an input or an output ?

Why was the 50MHz clock output mode chosen for the EVKB design ? Is this simply to avoid having a crystal on the PHY ?

Best Regards,

Pete.

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miduo
NXP Employee
NXP Employee

Hello,

Yes, your understanding is correct.