What does the LPSPI transmit data zero-extend feature do for MSB first?

[mitterha]

Hello,

the LPSPI Transmit Data Register TDR is built so that it zero-extends 8 and 16 bit writes

We want to fill the FIFO with DMA transfers. In case I have 5 bytes of data and a Framesize of 5 * 8 = 40 to send I will have one 4 byte DMA transfer and one 1 byte DMA transfer.

The last DMA transfer will only write 8 bit to the register therefore the bits 8 to 31 will be zero.

1. If the LPSPI module is set to MSB first will it send the zero data bits 24 to 31 instead of my expecet data?
2. If yes is it possible to write to bits 24 to 31 in TDR with DMA and will the lower bits automatically be 0 too?
3. Because of the limitation of DMA to 1,2 and 4 byte transfers it is not possible to send e.g. 3 bytes because I would have to write first 2 bytes to TDR (which will result in 2 zero bytes and 2 data bytes in TX FIFO) and then 1 byte (3 zero bytes in FIFO) which will result in at least 2 unwanted zero-bytes sent out through SPI right?

Kind regards,

Stefan

[Hui_Ma · Accepted solution]

Hi,

I did a test based on MCUXpresso SDK interrupt_b2b_master demo.

I make below change with the code:

uint32_t masterRxData[TRANSFER_SIZE] = {0U};

/*Master config*/
masterConfig.baudRate = TRANSFER_BAUDRATE;
masterConfig.bitsPerFrame = 40; //8;
masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
masterConfig.direction = kLPSPI_MsbFirst;

masterTxData[0] = 0x11223344;
masterTxData[1] = 0x55;

I could get below transfer siganl from captured scope:

So, the LPSPI module is set to MSB first it will send your expecet data.

Have a great day,
Mike

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[mitterha]

Thank you for testing it Mike!