Reception exception encountered during FlexCAN development using RT1176 CPU

[YueXia]

I encountered a situation when using RT1176 CPU for FlexCAN development, in the CAN receive part I use non-blocking receive, and use MB0 and MB1 to receive data, I found that when I received the data most of the MB0 processing, a very small part of the data is processed by MB1, but at a certain point in time to start the MB0 no longer carry out any processing, the data are all processed by MB1, and then run for a period of time after the MB1 counter is no longer accumulated. MB1 process, and then run for a period of time, MB1 counter is no longer accumulated, at this time to observe the MASK1 register value of 0x01, two mailboxes are normal when the value of the MASK1 register should be 0x03, and the value of the FLAG1 register has become 0x02, normally, when I complete a read, it will disable MASK1 and will clear FLAG1, so FLAG1 will be 0x02, and the value of FLAG1 will be 0x02. clear FLAG1, so the value of FLAG1 should be 0x00, then I changed the handling of FLAG in the FLEXCAN_ClearMbStatusFlags function.

The initial code:
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU);
base->IFLAG2 = (uint32_t)(mask >> 32);
#base->IFLAG1 = (uint32_t(mask & 0xFFFFFFFFU))
base->IFLAG1 = mask; #else
#endif

My modified code:
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
// base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU);
// base->IFLAG2 = (uint32_t)(mask >> 32);
base->IFLAG1 |= (uint32_t)(mask & 0xFFFFFFFFU);
base->IFLAG2 |= (uint32_t)(mask >> 32); base->IFLAG2 |= (uint32_t)(mask >> 32);
#else
// base->IFLAG1 = mask; base->IFLAG2 |= (uint32_t)(mask >> 32); #else
base->IFLAG1 |= mask; #else // base->IFLAG1 = mask.
#endif

After following this modification my MB counter is back to normal, Thank you in advance.

Best Regards,
LIU

i.MX-RT1170 

[YueXia]

后续发现不是因为这个位置导致，详细情况请见下一条帖子