RT 1020 Maximize DTC, at the cost of ITC and OC

[bp1979]

Dear nxp,

Can somebody please explain what the possibilities are wrt FlexRAM on a RT 1020?

I read in the 12077 AN that I can rearrange memory in two different ways. One way is using fuses, and another way is in software (during reset handler).

Since burning fuses is irreversible, I am not interested in that approach. So that would leave me to rearranging this during the reset handler.

I am trying to find extensive documentation on this topic, but it seems hard to find.

Who is willing to answer my questions?

- Is it correct that I ONLY need ITC in case I want to run code from SRAM? 

- Can I simply rearrange memory in MCU Xpresso's memory configuration wizard?

- What's the maximum possible amount of DTC memory on my chip? (meaning, can I set ITC and OC to zero e.g.? The AN claims that working with fuses a minimal amount of OC is set to 64K, is that also the case when rearranging memory in reset handler?)

- I can't imagine I am the only person struggling with this, is there detailed documentation on how to rearrange on chip memory? Or better.... an example?

- What's the purpose of OC memory to begin with? Why do I want it? When do I use it? Which memory is sent to OC, and why (why prefer OC over "optimized DTC")?

[kerryzhou · Accepted solution]

Hi @bp1979 

  About the flexRAM reconfiguration, it is not complicated, please refer to this document:

https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Reallocating-the-FlexRAM/ta-p/1117649

 And, from AN12077:

https://www.nxp.com/docs/en/application-note/AN12077.pdf

you also need to note:

1. OCRAM must leave 64KB for the ROM usage.

2. The Arm Cortex-M7 specifications require the size of ITCM/DTCM to be a power-of-two number, which can conflict with the FlexRAM configuration capability

So, from the table:

You want to use the max DTCM, you can use OCRAM 64KB, DTCM 128KB, ITCM 64KB.

Although the ITCM can be 0, but to the above 2 points, you just can use the OCRAM 64KB, DTCM 128KB, ITCM 64KB.

Then you can configure the register in the above link post sharing.

You can try it on your side, if you still have questions, please kindly let me know.

Please also note, in your application about the flexRAM configuration, you also need to modify the stack location to start:

Wish it helps you!

If you still have questions about it, please kindly let me know.

Best Regards,

Kerry

[bp1979]

delete me

[kerryzhou]

Hi @bp1979 , 

 In fact, you just need to check the AN12077 the table about the IOMUXC_GPR_GPR17:

Then use the related listed data is OK.

Eg, you choose: OCRAM 64, DTCM 128, ITCM 64, then your IOMUXC_GPR_GPR17 = 0xFAA5.

More details, check the AN chapter 2.1.2. Definition of the memory type size, you will be more clear.

n just means each back, and it will define the different RAM back as the different function, ocram, dtcm, or itcm.

Wish it helps you!

Best Regards,

Kerry

[bp1979]

Hi @kerryzhou 

Thanks for all your lengthy explanations. I am nearly there.

Just wanted to check the following with you.

In the article Reallocating the FlexRAM - NXP Community GPR14 describes the amount of memory assigned to DTC / ITC.

When I look in my RT 1020 RM, I have a completely different register:

Can you explain this? 

[bp1979]

Hi @kerryzhou 

Regardless of the (for me) weird definition of GPR14, your solution works.

It fails when I set ITC to 0, DTC to 192KB, and OC to 64KB. I get hard faults in that configuration. I'll revisit that later when my "more urgent topics" are covered.

the configuration that you suggested works fine (ITC 64, DTC 128, OC 64).

Many thanks for the links and the explanations! 

[kerryzhou]

Hi @bp1979 

   Just as my first email to tell you:

2. The Arm Cortex-M7 specifications require the size of ITCM/DTCM to be a power-of-two number, which can conflict with the FlexRAM configuration capability

  192K is not the power of two number, that's why I recommend you to use ITC 64, DTC 128, OC 64

Wish it helps you!

Best Regards,

Kerry