MIMXRT1170 Interrupt issue

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MIMXRT1170 Interrupt issue

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muratokusluk
Contributor II

Hi Everyone,

I want to ask something about GPIO external interrupt. In the MIMXRT1170_igpio_input_interrupt example, GPIO13_io0 pin is defined as input and is enabled rising edge interrupt. I want to GPIO8_io29 instead of GPIO13_io0. But I can't see any interrupt handler for gpio8.

How can I define gpio8_29 as external interrupt?

 

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @muratokusluk,

Although most of the pins are accessible by both the CM7 domain and the CM4 domain, GPIO7 through GPIO12 are all accessible only by the CM4 domain:

EdwinHz_5-1707351396046.png


GPIO8 is therefore only intended for CM4 access, so it does not have a CM7 interruption. Note how "Table 4-2. CM4 domain interrupt summary" from the Reference Manual has GPIO7 through GPIO11 on IRQ 99:

EdwinHz_6-1707351403332.png

But "Table 4-1. CM7 domain interrupt summary" has CM7_GPIO2 and CM7_GPIO3 IRQs instead:

EdwinHz_7-1707351418503.png

That said, GPIO_EMC_B2_19, which is the pad that routes GPIO8_IO29, also routes GPIO_MUX2_IO29 when using alt function 5 rather than 10:

EdwinHz_8-1707351431130.png
EdwinHz_9-1707351431131.png

Therefore, you can configure the pad and interruption for GPIO8 with IRQ 99 when using CM4 or configure the same pad and interruption for CM7_GPIO2 when using CM7, and the IRQ will continue being IRQ 99 (CM7_GPIO2).

If you base your project on ipgio_input_interrupt_cm4 rather than cm7, you will find "GPIO7_8_9_10_11_IRQHandler()" on startup_mimxrt1176_cm4.c

I hope this answers your question.

 

BR,
Edwin.

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Artos
Contributor I

I encountered the same problem. Is there any progress?

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muratokusluk
Contributor II

Thanks Edwin, I understand

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @muratokusluk,

Although most of the pins are accessible by both the CM7 domain and the CM4 domain, GPIO7 through GPIO12 are all accessible only by the CM4 domain:

EdwinHz_5-1707351396046.png


GPIO8 is therefore only intended for CM4 access, so it does not have a CM7 interruption. Note how "Table 4-2. CM4 domain interrupt summary" from the Reference Manual has GPIO7 through GPIO11 on IRQ 99:

EdwinHz_6-1707351403332.png

But "Table 4-1. CM7 domain interrupt summary" has CM7_GPIO2 and CM7_GPIO3 IRQs instead:

EdwinHz_7-1707351418503.png

That said, GPIO_EMC_B2_19, which is the pad that routes GPIO8_IO29, also routes GPIO_MUX2_IO29 when using alt function 5 rather than 10:

EdwinHz_8-1707351431130.png
EdwinHz_9-1707351431131.png

Therefore, you can configure the pad and interruption for GPIO8 with IRQ 99 when using CM4 or configure the same pad and interruption for CM7_GPIO2 when using CM7, and the IRQ will continue being IRQ 99 (CM7_GPIO2).

If you base your project on ipgio_input_interrupt_cm4 rather than cm7, you will find "GPIO7_8_9_10_11_IRQHandler()" on startup_mimxrt1176_cm4.c

I hope this answers your question.

 

BR,
Edwin.