MIMXRT1170 Interrupt issue

[muratokusluk]

Hi Everyone,

I want to ask something about GPIO external interrupt. In the MIMXRT1170_igpio_input_interrupt example, GPIO13_io0 pin is defined as input and is enabled rising edge interrupt. I want to GPIO8_io29 instead of GPIO13_io0. But I can't see any interrupt handler for gpio8.

How can I define gpio8_29 as external interrupt?

[Artos]

I encountered the same problem. Is there any progress?

[muratokusluk]

Thanks Edwin, I understand

[EdwinHz · Accepted solution]

Hi @muratokusluk,

Although most of the pins are accessible by both the CM7 domain and the CM4 domain, GPIO7 through GPIO12 are all accessible only by the CM4 domain:

GPIO8 is therefore only intended for CM4 access, so it does not have a CM7 interruption. Note how "Table 4-2. CM4 domain interrupt summary" from the Reference Manual has GPIO7 through GPIO11 on IRQ 99:

But "Table 4-1. CM7 domain interrupt summary" has CM7_GPIO2 and CM7_GPIO3 IRQs instead:

That said, GPIO_EMC_B2_19, which is the pad that routes GPIO8_IO29, also routes GPIO_MUX2_IO29 when using alt function 5 rather than 10:

Therefore, you can configure the pad and interruption for GPIO8 with IRQ 99 when using CM4 or configure the same pad and interruption for CM7_GPIO2 when using CM7, and the IRQ will continue being IRQ 99 (CM7_GPIO2).

If you base your project on ipgio_input_interrupt_cm4 rather than cm7, you will find "GPIO7_8_9_10_11_IRQHandler()" on startup_mimxrt1176_cm4.c

I hope this answers your question.

BR,
Edwin.

[mimlo]

Hi @EdwinHz,
I recently saw this answer you gave and started wondering whether it's actually true as something was off for me.

You stated that "GPIO7 through GPIO12 are all accessible only by the CM4 domain", so I started looking through RM and I found the following:

The description of AIPS-4 clearly says that this memory map range is accessible by both CM7 and CM4 cores. So from my understanding, it stands in contradiction with what you stated some time ago.

What is more, I think the Bus Diagram that you pasted, actually has a bus connection to the GPIO[12-7] through the following route (provided that my understanding is correct):

I sort of assumed the flow looks like that based on the information from RM that says those PGIOs are accessible. Please correct me if I'm wrong but something is definitely off and I feel it should be straightened out.

Best Regards,
Michael