Hello,
we’re testing flexspi in the following configuration:
static inline void FLEXSPI_ClockInit(void)
{
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24); /* Set PLL3 PFD0 clock 360MHZ. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x0); /* Choose PLL3 PFD0 clock as flexspi source clock. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, divider);
}
and measuring frequency. For divider 2 the frequency is ~25MHz, and for divider 7 the frequency ~9MHz.
We’re interesting to reduce the frequency to ~3MHz, is there is any way to do it?
Thanks!
Adi,
Intel
Hi @adi2Intel ,
About the flexspi clock setting, you totally can use the MCUXPresso IDE CFG clock to configure it:
The divide max is 8, if after 8 divider, still can't match your required frequency.
Then you need to cut down the flexSPI source code, just use the CFG tool to configure it, more easy.
Best Regards,
Kerry