lpspi_interrupt_b2b_master example code concerns

[patrick_yang]

Hello,

The lpspi_interrupt_b2b_master.c example code confused me about the transfer data frame size and transfer fifo size.

In LPSPI_MasterInit(), the TCR is configured to be the default data frame size, which is 8.  Did not find other statements to change the data frame size to word or 32 bits.  Also

g_masterFifoSize = LPSPI_GetRxFifoSize(EXAMPLE_LPSPI_MASTER_BASEADDR);

where g_masterFifoSize is 16, which shall be 16 * 4 = 64 bytes per the NXP explanation: 

https://community.nxp.com/t5/i-MX-RT/iMX-RT1064-LPSPI-Maximum-FIFO-Size/m-p/915843

Below are the confusion statements in the code:

/* Fill up the TX data in FIFO. */
while ((LPSPI_GetTxFifoCount(EXAMPLE_LPSPI_MASTER_BASEADDR) < g_masterFifoSize) &&
(masterTxCount - masterRxCount < g_masterFifoSize))
{
/*Write the word to TX register*/
LPSPI_WriteData(EXAMPLE_LPSPI_MASTER_BASEADDR, masterTxData[masterTxCount]);
++masterTxCount;

if (masterTxCount == TRANSFER_SIZE)
{
break;
}
}

Per the commend, the LPSPI_WriteData() write a word instead of a byte each time.  Per the statements ++masterTxCount; and if (masterTxCount == TRANSFER_SIZE), the LPSPI_WriteData() seems write a byte each time.

If LPSPI_WriteData() writes a byte each time and the FIFO buffer size is 64 bytes or 16 words, why using (masterTxCount - masterRxCount < g_masterFifoSize)?  Should it be (masterTxCount - masterRxCount < g_masterFifoSize * 4)?

Thank you in advance for any responses.

Patrick

[jeremyzhou · Accepted solution]

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Firstly, the FIFO depth is 16, and it can store up to 64 bytes, secondly, both 8-bit and 16-bit writes of transmitting data will zero-extend the data written and push the data into the transmit FIFO which is as same as write 32 bit to TDR register.
Hope this is clear.
Have a great day,
TIC

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[patrick_yang]

Hi, jeremyzhou,

Thank you very much for the prompt clarification!

Patrick