Was working on a new platform design using the iMXRT1062. Was working as expected with 128MB but when I went to a 256MB and 512MB flash, things started breaking. Assumed it was the 3 byte and 4 byte addressing issue but am having trouble reading the bank config register to set 4 byte mode. I modified the flexspi_nor_polling_transfer example application to test out access but does not seem to work. Perhaps someone can see what is in error
Additions to LUT
/* Write Bank register */
[4 * NOR_CMD_LUT_SEQ_IDX_WRITE_BANKREG] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x17, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x01),
/* Write NV Bank register */
[4 * NOR_CMD_LUT_SEQ_IDX_WRITE_NVBANKREG] =
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x18, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x01),
Bank register write procedure:
status_t flexspi_nor_bank_vwrite(FLEXSPI_Type *base, flexspi_port_t port, uint8_t vol, uint8_t writeData)
{
uint8_t seq = vol;
status_t status;
flexspi_transfer_t flashXfer;
flashXfer.deviceAddress = 0;
flashXfer.port = port;
flashXfer.cmdType = kFLEXSPI_Write;
flashXfer.SeqNumber = 1;
flashXfer.seqIndex = vol;
flashXfer.data = writeData;
flashXfer.dataSize = 1;
/* Write neable */
status = flexspi_nor_write_enable(base, 0);
if (status != kStatus_Success)
{
return status;
}
status = FLEXSPI_TransferBlocking(base, &flashXfer);
if (status != kStatus_Success)
{
return status;
}
status = flexspi_nor_wait_bus_busy(base, kFLEXSPI_PortA1);
return status;
}
