I need to read data from SDRAM noncache area.the SDRAM is simulated using FPGA,and it contains ADC result,so it must have noncache attribute.
The problem is that it consumes about 1.5us to read 10 uint16_t data.Using FPGA to monitor data transfering on the bus,it shows like the picture below
There are about 26 clocks between two read operation,and during this period,the bus is idle.My CPU works at 528MHz,and SEMC works at 132MHz。
The disassember code that read data from FPGA is listed below:
mov.w r3,0x84000000
add.w r4,r7,#8
mov r5,r3
ldr r0, [r5, #0]
ldr r1, [r5, #4]
ldr r2, [r5, #8]
ldr r3, [r5, #12]
stmia r4!,{r0,r1,r2,r3}
ldr r0,[r5,#16]
str r0,[r4,#0]This code segment locates in the highest priority ISR,There is no possible to be interrupted.
why are there 26 clocks between two read operation?How can i promote reading speed?
Any suggestion is appreciated!
Thanks in advance.
Best regards!
