RT117x DCD Table Configuration

[Wobaffet]

Hello, 

For our custom board, we will be using EM638165BM-5IH 54-FBGA (8x8) as an SDRAM from Etron, 64Mbit (4Mx8) version of this one from Digikey.  Basically, RAMs will be different from the evaluation kit or SLN-TLHMI kit but the connections will be the same with the SLN-TLHMI kit. So how can we configure the DCD table, what are the things that we need to be aware of?

Thank you in advance!

Best Regards.

[Wobaffet]

Hello Kerry,

We have a problem with our custom board, when we move the BOARD_SDRAM section right after flash, board crashes. We have to do full chip erase in order to program again. But in the below configuration everything seems to working fine like I mentioned earlier test code for the sdram works but when we move sdram upto the second place nothing works. Also the reason we are trying to move the external ram section into the second place is to configure a frame buffer. Do you have any idea what causes this problem?

Best Regards,

[kerryzhou]

Hi @Wobaffet ，

   Sorry for the later reply.

   To the new question, could you please help to create a new question post about it, then we will help you in your new question post, thanks, don't update the old case, as that is closed, thanks.

Best Regards,

kerry

[Wobaffet]

Hello Kerry, my new post is here. Can you check if you are available?

thank you in advance!

[Wobaffet]

Thank you for the heads-up I've posted as a new question. 

Best Regards.

[Wobaffet]

Hello Kerry,

We verified our SDRAM works with configured parameters on the above code and on the example you've mentioned. My question is whether DCD is necessary, what is the purpose of the DCD table because the example project does not have one? Can't we just use the configuration code above?

Thank you in advance! 

Best Regards.

[Wobaffet]

reminder

[kerryzhou · Accepted solution]

Hi @Wobaffet ,

   Good question, sorry for my later reply.

   DCD is used to configure the SDRAM during the boot, then in your app code, you can use the SDRAM directly, eg, some code or data need to copy to the SDRAM remap address, then your app can use it directly, you don't need to use the app code to init the SDRAM like your first post.

   So, if your SDRAM is make sure working, then you can add the related configuration to the DCD area, the your app can use the SDRAM address as the RAM area directly.

   For the DCD configuration, you can refer to the RT1170 RM, chapter 10.7.2 Device Configuration Data (DCD).

  About the demo code, you can refer to the SDK any demo code, the DCD.c is used to configure the EVK on board SDRAM.

  BTW, if you use the above code to configure the SDRAM in the app, it's also OK.

  Wish it helps you!

Best Regards,

Kerry

[kerryzhou]

Hi @Wobaffet ,

   At first, I think, what's important to you is not the DCD, you need to test your SDRAM works OK.

  \SDK_2_13_10_MIMXRT1170-EVK\boards\evkmimxrt1170\driver_examples\semc\sdram\cm7

  You can test this code.

   After it works, then you can modify the DCD related configuration.

   Normally, you need to modify the SDRAM init code which matches your used SDRAM datasheet, I mean this code:

status_t BOARD_InitSEMC(void)
{
    semc_config_t config;
    semc_sdram_config_t sdramconfig;
    uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;

    /* Initializes the MAC configure structure to zero. */
    memset(&config, 0, sizeof(semc_config_t));
    memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));

    /* Initialize SEMC. */
    SEMC_GetDefaultConfig(&config);
    config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
    SEMC_Init(SEMC, &config);

    /* Configure SDRAM. */
    sdramconfig.csxPinMux           = kSEMC_MUXCSX0;
    sdramconfig.address             = 0x80000000;
    sdramconfig.memsize_kbytes      = 2 * 32 * 1024;       /* 64MB = 2*32*1024*1KBytes*/
    sdramconfig.portSize            = kSEMC_PortSize32Bit; /*two 16-bit SDRAMs make up 32-bit portsize*/
    sdramconfig.burstLen            = kSEMC_Sdram_BurstLen8;
    sdramconfig.columnAddrBitNum    = kSEMC_SdramColunm_9bit;
    sdramconfig.casLatency          = kSEMC_LatencyThree;
    sdramconfig.tPrecharge2Act_Ns   = 15; /* tRP 15ns */
    sdramconfig.tAct2ReadWrite_Ns   = 15; /* tRCD 15ns */
    sdramconfig.tRefreshRecovery_Ns = 70; /* Use the maximum of the (Trfc , Txsr). */
    sdramconfig.tWriteRecovery_Ns   = 2;  /* tWR 2ns */
    sdramconfig.tCkeOff_Ns =
        42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
    sdramconfig.tAct2Prechage_Ns       = 40; /* tRAS 40ns */
    sdramconfig.tSelfRefRecovery_Ns    = 70;
    sdramconfig.tRefresh2Refresh_Ns    = 60;
    sdramconfig.tAct2Act_Ns            = 2; /* tRC/tRDD 2ns */
    sdramconfig.tPrescalePeriod_Ns     = 160 * (1000000000 / clockFrq);
    sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
    sdramconfig.refreshUrgThreshold    = sdramconfig.refreshPeriod_nsPerRow;
    sdramconfig.refreshBurstLen        = 1;
    sdramconfig.delayChain             = 6; /* For all tempeatures. */

    return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);
}

Please try it on your side.

Best Regards,

Kerry