Hello all,
We are having difficulties with the SDRAM of our second generation of custom rt1064 board. Additionally, we are using the same SDRAM as the EVK.
There is no difference in design, position & rouring of the MCU & SDRAM module compared to the first generation.
However, first we noticed that the MCU would not boot on Zephyr RTOS and then testing it on MCUXpresso with SEMC sample we noticed that the first write/read always fails and the write/read only works properly after the second write/read.
Any help would be appreciated!
SEMC SDRAM Example Start!
SEMC SDRAM Memory 32 bit Write Start, Start Address 0x80000000, Data Length 4096 !
SEMC SDRAM Read 32 bit Data Start, Start Address 0x80000000, Data Length 4096 !
SEMC SDRAM 32 bit Data Write and Read Compare Start!
SEMC SDRAM 32 bit Data Write and Read Compare Failed!
SEMC SDRAM Memory 32 bit Write Start, Start Address 0x80000000, Data Length 4096 !
SEMC SDRAM Read 32 bit Data Start, Start Address 0x80000000, Data Length 4096 !
SEMC SDRAM 32 bit Data Write and Read Compare Start!
SEMC SDRAM 32 bit Data Write and Read Compare Succeed!
SEMC SDRAM Example End.
Hello
Could you attach some scopes to check the signal integrity? If design, routing and position is the same as the EVK it should not fail. What is the IO configuration?
Best regards,
Omar
@Omar_Anguiano Thank you for your reply.
Unfortunatelly, we cannot test the signal integrity because there is no test pads on the board
Below is the IO of the SDRAM. The only difference compared to the previous generation that everything works is the LED at GPIO_EMC_39. We also tried to remove the resistor and let the pin float like before, but it did not change anything.
Kind regards,
Mario
After some more tests (flashing with zephyr rtos images) we noticed that on the board with the LED on EMC_39. "hello_world" sample would boot and it would properly run for maximally 1 minute and then it would output nonsense data.
Meanwhile the board with EMC_39 floating it would not boot at all.
Both boards have still issues with the semc sample
If you use MCUXpresso, does the issue persist?
If external signal delay is big, it has the complicated topology and long trace, so it can't take DQS pad delay to compensate external SDRAM signal delay, so it need to add additional capacitance on DQS pin for compensation.
Also it is hard to give the guide on what capacitance is good, as this is related to SDRAM signal layout, different layout will get the different signal delay.
Best regards,
Omar