Hi, I'm now using RT1176 as our control unit. In order to get more performance in our product, we have added a FPGA on our board. They communicate with each other through SEMC in synchronized ADMUX SRAM mode, but I have several issues about the timing diagram.
How should I configure this interface in synchronized ADMUX SRAM mode, or can you post me with a reference?
I have read many documents and found that there is almost no reference about synchronization SRAM mode. When I read the SDK(fsl_semc.h), I have found many configuration items about the timing, but the offical manual only refers to CES, CEH, AS, LC and RD in our mode. Do the other options such as tAddrHold_Ns and tWriteSetup_Ns need to be configured?
2. I understand that the Read time can be configured by SRAMCR2[RD]. And if that the vaule is set to 2 clock cycles, when does DQS sampling pulse occur?
I have drawn my guess in the diagram, and the green line acts as the capture edge, the red box acts as the data range. The timing diagram in 2 clock cycles is right or not?
Hi @raincorn233 ,
1 tAddrHold_Ns should be AH. But I don't know what is tWriteSetup_Ns. You can refer to these diagram.
2. Yes, correct.
Regards,
Jing
