Hi,
I would like to communicate with pipeline ADC using RT1052, the interface is parallel digital output. just like following timing diagram. All the data bits are synchronized with clk, It should sample the dates on the raising edge of the clk.
My demand:
The maximum clk frequency is 20Mhz.
16bits or 8bits data width.
Continuously buffer at leat 1k data from ADC with maximum 20Mhz frequency, and store the data in the SDRAM.
I am confused how to achieve that. Should I use CSI interface or Flexio interface?
What example is the closest one that I can refer?
Another questions from RT1052 reference manual about FLEXIO interface.
The manual set an example for 8bits CMOS sensor application using FLEXIO parallel interface.
I did not quite understand about it, what's the purpose of configuring SHITER0,1,2 to adjacent shiter?
And how to use DMA work with flexio interace, is there any example?
Thanks a lot for your support.
