IMXRT1064 Sequential Read Operation Problem

[Lukas_Frank]

Hi Dear Authorized,

I have SRAM-FPGA application. I am able to read and write data from/to FPGA. IMXRT1064 MCU will be used as Master and FPGA will be Slave. I said that able to read/write but the read operation is only achieved by once. I am not able to achieve sequential read operations. My base address is 0x90000000 and it is only updated for once when the BOARD_InitSRAM function is executed. 

We are expecting that SEMC Memory (0x90000000) memory refreshed with new FPGA data after Read Code is run. But the semc memory is only refreshing after init sram with BOARD_InitSRAM function. When the SEMC_ConfigureSRAM function is finished memory is fulfilling with FPGA datas. It is exactly happening when the base->BR[6] = tempBRVal; line is executed. Why we are not able to request data from FPGA in sequential order when we access memory?

I want exactly reading 64-Byte new data from FGPA when I run SEMC_SRAMRead32Bit function. What is the way of reading sequential data from FPGA? How did you read data chunks in sequential order again and again?

Read Code:

void SEMC_SRAMRead32Bit(void)
{
    uint32_t index;
    uint32_t datalen = SEMC_EXAMPLE_DATALEN; //SEMC_EXAMPLE_DATALEN=64
    uint32_t *sram  = 0x90000000

    for (index = 0; index < datalen; )
    {
    	sram_readBuffer[index++] = sram[index];
    }

}

Thanks and Regards.

[Hui_Ma]

Hi,

I would recommend customer to refer below sharing:

https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/How-to-configure-SRAM-in-SEMC-modules-for-RT-dev...

The SRAM interface supports 16 bit mode, could you try to do the uint16(unsigned short) data operation.

Mike

[Lukas_Frank]

Hi Dear @Hui_Ma ,

I am working for 3 weeks. Nothing is changed. There is no read operation in the example you shared. It uses different style.

Do we have another approach?

Thanks and Regards.

[Hui_Ma]

Hi Lucas,

First of all, sorry for the later reply.

I did not find there with any SEMC read issue with external SRAM.

About SEMC read code, please refer SEMC SDRAM, should be same：

void SEMC_SDRAMReadWrite32Bit(void)
{
    uint32_t index;
    uint32_t datalen = SEMC_EXAMPLE_DATALEN;
    uint32_t *sdram  = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
    bool result      = true;

    /* Read data from the SDRAM. */
    for (index = 0; index < datalen; index++)
    {
        sdram_readBuffer[index] = sdram[index];
    }
}

best regards,

Mike

[Lukas_Frank]

Hi Dear @Hui_Ma ,

You are right. I am able to read data by using this pointer arithmetic approach. When I use like the code you shared, the FPGA is triggering and sending data to IMXRT.

But the critical point is that ADDR is always start from 0x0000 and it is increasing in incremental order. 0x0000, 0x0001, 0x0002, 0x0003 and 0x000n where the "n" is read request length(datalen).

I want to learn if the ADDR (Address) register associated with the SEMC interface is always starting from 0x0000 regardless of how you set your pointer arithmetic and it is controlled by SEMC controller in the hardware side in a way that incrementing the address automatically based on its own memory access pattern. Or I want to learn if it is possible.

How can I set ADDR to start from specific address value like 0xFFA2. Is it possible to achieve?

Thanks and Regards.

[Hui_Ma]

Hi,

SEMC should support customer to read external RAM memory from any valid address range, such as  0x9000_FFA2. Even SEMC will read from an unalignment address, that read operation just add read cycles with low efficiency.

Please first to check if using pointer to read external RAM memory. If you could read some data back from external memory? If yes, then we can go deep why related data were incorrect.

Please show us an example, if you using pointer way to read data from external RAM memory, what data read, while the real data should be? Thanks for the attention.

Mike 

[Lukas_Frank]

Hi Dear Mike @Hui_Ma ,

Actually my case is based on reading data from FPGA which is connected physically to the IMXRT with ADDR, DATA, BA1, CE, CLK, DQS, RDY, CSX pins.

I am able to operate read and write functions sequentially between IMXRT(Master)-FPGA(Slave).

My main issue is; in the FPGA side, ADDR register value is always starting from 0x0000 and continues in incremental order like below:

0x0000, 0x0001, 0x0002, 0x0003, ....... 0x000n. The n represents how many bytes which I requested from FPGA in the IMXRT side.

I just want to configure my system in a way that ADDR can be able to start from specific address like 0x00FF or 0x00A3 or 0x07B2 and continue in incremental order to the end of ADDR bit valid threshold.

Examples about what I want to do:

Example 1 - Start ADDR Configured as 0x00FF and 6 x 16 bit is sended to FPGA:

Expected ADDR view in the FPGA Signal Analyzer:
0x00FF - 0x0100 - 0x0101 - 0x0102 - 0x0103 - 0x0104

Monitored ADDR view in the FPGA Signal Analyzer:
0x0000 - 0x0001 - 0x0002 - 0x0003 - 0x0004 - 0x0005

Example 2 - Start ADDR Configured as 0x1F00 and 9 x 16 bit is sended to FPGA:

Expected ADDR view in the FPGA Signal Analyzer:
0x1F00 - 0x1F01 - 0x1F02 - 0x1F03 - 0x1F04 - 0x1F05 - 0x1F06 - 0x1F07 - 0x1F08

Monitored ADDR view in the FPGA Signal Analyzer:
0x0000 - 0x0001 - 0x0002 - 0x0003 - 0x0004 - 0x0005 - 0x0006 - 0x0007 - 0x0008

Here is how I read the data in the code side:

void SEMC_SRAMRead16Bit(void)
{
    uint32_t index;

    uint32_t datalen = 5; //9

    uint32_t *sram  = (uint16_t*)0x90000000

    for (index = 0; index < datalen; index++)
    {
    	sram_readBuffer[index] = sram[index];
    }

}

I am reading data successfully but I just want to use the ADDR value's address space efficiently to address multiple transaction with defined identifications. Therefore, I need to configure my code in a way that ADDR register can be monitored with a specific start address like examples above.

Update:

I found a workaround by trial. I am increasing SRAM index by starting a specific address and now it ensures what I want as defined in examples(Expected Case). But I am curious if it is official or not.

Now I am curious about. What is the official way of increasing ADDR from specific start value?

Thanks and Regards. 

[Hui_Ma · Accepted solution]

Hi,

Please refer below code to read data from external memory.

#define BUFFER_SIZE_BYTE          0x10
UINT32 programvalue[BUFFER_SIZE_BYTE];
                for (i = 0; i<BUFFER_SIZE_BYTE; i=i+4)
                {
                    programvalue[i] = *((UINT32 *)(destination+i)) ;
                    printf("\n programvalue[%d] = 0x%4x \n", i, programvalue[i]);

                }

with it helps.

Mike