We have prototypes of our RT1062 design with octal hyperflash and octal hyperram (2 die in one package) and I am working on software. The two devices use FLEXSPI A and B data[3:0], and FLEXSPI_A_SS0_B, FLEXSPI_A_SS1_B, as in fig 27-3 of the RT1060 reference manual. We would like to boot & run XIP on the hyperflash, and ideally access the hyperram via AHB for general data storage/buffer.
I have code running XIP from the hyperflash, but don't quite have the hyperram running yet. IP write/read does not give the same data, and AHB accesses cause a hardfault / bus error. I note these two posts
https://community.nxp.com/t5/i-MX-RT/Question-about-Using-HyperRam-and-HyperFlash/m-p/971681
https://community.nxp.com/t5/i-MX-RT/How-can-use-the-HyperRAM-and-Qual-SPI-Flash-in-i-MXRT1052/m-p/1...
and would like to get some confirmation that what I am trying to do is possible before I spend too much time trying to get it to work. I cannot find any information in the Reference Manual or Errata that suggests running XIP precludes the use of a second device on the FLEXSPI in octal mode, with AHB access.
Can anyone authoritatively confirm that operation of two octal hyperbus devices on the 1062 FLEXSPI is possible or not, with XIP for one device, and AHB access on the other? (If not possible, perhaps this should be noted in the Reference Manual or Errata?)
Cheers,
Mark
