Hi guys,
I'm new on the i.MX RT boards, but I'm quite familiar with Arm Cortex-M processors, specially TrustZone-enabled ones (CM33, CM32).
When I started reading the RM and Security-RM docs of i.MXRT1020 I caught some references to some TrustZone terminology, which confused me. Moreover, I don't quite capture what is the big difference between the CSU and AIPSTZ, where supposedly all magic happens. And, there are also some references to resource domains and the RDC submodule, which I can't find any documentation on the i.MXRT1020 docs (so, I suppose it's some miscopy from other i.MX reference manuals).
All these doubts, have raised me several questions, which I hope you can answer me:
1) Arm CM7 platform is a non-TrustZone enabled core. But, as far I understand, the CSU and AIPSTZ define access control policies based upon secure/non-secure state, and even supervisor/user privilege. From what I read, a master can be defined with these attributes through two registers: the CSU_SA and the AIPSTZx_MPR register. Is this overlapped? Or does each register configures different bus master groups?
2) Regarding CSU and AIPSTZ components, both feature registers to determine the read and write access permissions for slave peripherals (CSU_CSL and AIPSTZx_OPACR, respectively). Both seem to conceptually do the same thing, and looking to the affected peripherals, the list is the same. So, what is the difference?
3) Is there any more detailed block diagram to have a better understanding to where does it components sits on the SoC?
I guess what I'm really looking is to understand the real difference between the CSU and AIPSTZ, which access control each one applies and which bus masters and slaves they affect.
Thanks
