Hi,
MIMXRT1051CVL5B.
We want to support Jtag (bit-bang) and UART (dedicated), which will be routed from the NXP MCU to the same connector in our design. The user will choose by FW, on the fly, the interface he wants to use- UART/Jtag.
We will do HW shorts from the NXP Jtag pins to the NXP UART pins (see picture below):
GPIO_EMC_17 (UART CTS) will be shorten to GPIO_EMC_16 (bit-bang Jtag DO)
GPIO_EMC_18 (UART RTS) will be shorten to GPIO_EMC_15 (bit-bang Jtag DI)
GPIO_EMC_19 (UART TX) will be shortened to GPIO_EMC_13 (bit-bang Jtag Clk)
GPIO_EMC_20 (UART RX) will be shorten to GPIO_EMC_27 (bit-bang Jtag SS)
Is it possible to support that function in the NXP MCU? Do you see any constraint to keeping that? Will the pin that is not in use affect the pin that is used?
For example, when we use GPIO_EMC_17, migth GPIO_EMC_16 affect the GPIO_EMC_17 interface?
Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Is it possible to support that function in the NXP MCU? Do you see any constraint to keeping that? Will the pin that is not in use affect the pin that is used?
-- To be honest, I'm not 100% sure, as the pin that is not in use definitely affects the pin that is used, as every pin has its electrical attribution configuration, further, I'm confused with the above Jtag pins, they shouldn't work as the JTAG pins actually.
Have a great day,
TIC
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