set CCM_CLKO1 to 11.2896MHzMHz

[强王]

in 3.10.53 kernel:

CCM_CLKO1（audio i2s master）is 24MHZ ,   how to set to 11.2896MHzMHz

I change

imx_clk_set_rate(clk[pll4_audio_div], 541900800);

to

imx_clk_set_rate(clk[pll4_audio_div], 90316800); //8*11289600

question:

clk_get_rate(data->codec_clk) print the value is 11289600,

but the clock is still 22.5MHZ(11289600*2) by  oscilloscope

[saurabh206]

Hi

Qiang

What is your kernel version?

For Linux Kernel 3.0.35

you can refer arch\arm\mach-mx6\clock.c

clk_set_rate().

Thanks

Saurabh

[强王]

in 3.10.53 kernel:

CCM_CLKO1（audio i2s master）is 24MHZ ,   how to set to 11.2896MHzMHz

I change

imx_clk_set_rate(clk[pll4_audio_div], 541900800);

to

imx_clk_set_rate(clk[pll4_audio_div], 90316800); //8*11289600

question:

clk_get_rate(data->codec_clk) print the value is 11289600,

but the clock is still 22.5MHZ(11289600*2) by  oscilloscope

[saurabh206]

Hi Qiang

Which clock you are measuring MCLK or Bit clock? if it is bit clock (SSI clock) than output clock is divided based on DIV2, PSR and PM parameter configuration.

You can check

[强王]

HI Saurabh:

     Could you upload the document of this picture

[saurabh206]

Hi Qiang

Please refer "IMX6DQRM.pdf"

60.7.4 SSI Clocking

Thanks

Saurabh

[gusarambula]

Thank you, Saurabh, for the help! I'm sure this information will help other users of the communities.

[强王]

HI Saurabh and gusarambula:

I don't quite understand this picture

Can you tell me the code after the modification

[强王]

HI Saurabh:

the board is imx6q sabresd

i  measure GPIO_0