opp-suspend defined in all imx8mn operating points

[moose]

According to Generic OPP Bindings, listing `opp-suspend` property in all operating points will force the one with the highest running clock. In a53_opp_table node defined within imx8mn.dtsi, `opp-suspend` is listed in all operating points. Wouldn't this select the 1.5GHz operating during suspend? If yes, shouldn't `opp-suspend` only be listed within the 1.2GHz point?
 

a53_opp_table: opp-table {

compatible = "operating-points-v2";

opp-shared;

opp-1200000000 {

opp-hz = /bits/ 64 <1200000000>;

opp-microvolt = <850000>;

opp-supported-hw = <0xb00>, <0x7>;

clock-latency-ns = <150000>;

opp-suspend;

};

opp-1400000000 {

opp-hz = /bits/ 64 <1400000000>;

opp-microvolt = <950000>;

opp-supported-hw = <0x300>, <0x7>;

clock-latency-ns = <150000>;

opp-suspend;

};

opp-1500000000 {

opp-hz = /bits/ 64 <1500000000>;

opp-microvolt = <1000000>;

opp-supported-hw = <0x100>, <0x3>;

clock-latency-ns = <150000>;

opp-suspend;

};

};

[joanxie]

the driver would change the frequency Dynamically, you don't need change the table by youself

[moose]

Agreed. The question is what frequency would the driver choose in suspend mode. 

[joanxie]

for suspend mode, the arm core is power-gated

Suspend mode
This mode is called either Dormant mode or Deep sleep mode in the Linux BSP. This is the lowest possible power state where the external supplies are still on.
The use case is as follows:
• The Arm platform is power-gated.
• The L2 Cache peripherals are power-gated.
• The Arm Cortex-M4 is in the reset status.
• All PLL (Phase-Locked Loop) and CCM (Clock Controller Module) generated clocks are OFF.
• The CKIL (32 kHz) input is on.
• All modules are disabled.
• The external high-frequency crystal and the on-chip oscillator are powered down (by asserting the SBYOS bit in the CCM).